Active Gate Contact Interconnect for 6T SRAM Yield
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Solution Overview
Problem
Aggressive scaling of six-transistor static random access memory (6T SRAM) bitcells leads to decreased contacted polysilicon pitch (CPP) between gate electrodes, increasing the risk of adjacent gate electrode shortages and functional loss due to conventional contact interconnect formation techniques.
Innovation Solution
The method involves forming active contacts and gate contacts with approximately equal surface areas and using a first metal wire in a first metal layer to electrically connect them, thereby reducing the risk of gate electrode shortages and improving the parametric yield of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If current contact interconnect formation techniques (gate-active contact overlap) are used, then device scaling is achieved, but the risk of adjacent gate electrode shortages increases
Solution Approach 1:
The patent divides the contact formation process into separate gate contacts and active contacts, eliminating the overlap requirement. Each contact is formed independently with its own contact hole, preventing the shortage issue that arises from overlapping contacts while maintaining device scaling benefits
Solution Approach 2:
The patent introduces an intermediary metal layer (first metal layer) that provides alternative interconnection paths between gate electrodes and active regions. This intermediary layer allows routing around potential shortage areas, ensuring reliable electrical connection even when direct contact overlap would be problematic
2Adaptability or versatility
If contacts of varying shapes and sizes are used, then layout flexibility is achieved, but parametric yield loss occurs
Solution Approach 1:
The patent employs contacts of uniform size and shape (matching contact holes) throughout the device, eliminating the parametric variations that cause yield loss. This homogeneous approach maintains manufacturing precision while still achieving layout flexibility through the separated contact architecture and metal layer routing
3Reliability
If contact overlap is required, then electrical connection is achieved, but additional processing steps are needed
Solution Approach 1:
By segmenting the connection into separate gate contacts and active contacts that do not require overlap, the patent eliminates the need for additional alignment and formation steps. Each contact can be formed independently, streamlining the fabrication process while maintaining reliable electrical connections
Solution Approach 2:
The patent forms gate contacts and active contacts as separate preliminary structures before final interconnection. This preliminary separation allows each contact to be optimized and formed independently, reducing subsequent processing complexity and eliminating the need for overlap-based connection steps
Data Source
AI summary
A method of forming an active contact-gate contact interconnect including forming a first gate contact to a first gate electrode in an active region in a substrate, forming a first active contact to another portion of the first active region. The first gate contact and the first active contact include an approximately equal surface area, and forming an interconnect between the first active contact and the first gate contact. The interconnect includes a first metal wire in a first metal layer electrically connecting the first active contact to the first gate contact. The method may also include forming a second metal wire in the first metal layer configured to electrically connect a third metal wire in a second metal layer to an external contact to a second active region in the substrate, the external contact including the approximately equal surface area.