Active Gate Contact Structure for Smaller Tri-Gate Cell Layouts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor manufacturing is the trade-off between critical dimension and spacing of features in multi-gate transistors, particularly in tri-gate transistors, which limits the ability to form gate contacts over active regions without increasing transistor dimensions or requiring tight registration budgets.
Innovation Solution
The fabrication of gate contact structures over active portions of gate electrodes is achieved by forming trench contact vias and gate contact vias in the same layer, eliminating the need for additional gate contact layers and allowing direct contact from a metal interconnect layer on active gate portions, using self-aligned processes and selective etching techniques to align with existing gate patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate contacts are formed over active regions using conventional processes, then contact alignment precision is improved, but transistor dimension scaling is limited due to lithographic constraints
Solution Approach 1:
The patent moves the gate contact formation from the planar layout dimension to the vertical dimension by forming contacts through the interlayer dielectric layer directly over the active gate portions. This allows contacts to be established without consuming additional lateral space, enabling continued transistor scaling while maintaining alignment precision through self-aligned processes.
Solution Approach 2:
The gate contact formation process utilizes the existing gate structure and patterning as a self-aligned reference. The contact holes are formed to align with the active gate portions without requiring separate lithographic alignment steps, as the gate structure itself defines the contact location. This self-alignment mechanism maintains precision while enabling smaller transistor dimensions.
2Reliability
If additional gate contact layers are used to achieve reliable contact, then contact reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the gate contact formation with the existing contact hole formation process. The same contact holes that provide access to source and drain regions also provide access to the gate electrode, eliminating the need for separate gate contact layers. This consolidation maintains contact reliability by using the same proven contact formation process while reducing overall device complexity.
Solution Approach 2:
The contact holes formed in the interlayer dielectric layer serve multiple functions simultaneously: they provide electrical access to the source/drain regions and also provide access to the gate electrode for gate contact formation. This multi-functional approach eliminates redundant structures and reduces device complexity while maintaining all necessary electrical connections.
3Ease of manufacture
If extended gate lines on isolation are used to form contacts, then contact formation ease is improved, but standard cell area increases
Solution Approach 1:
Instead of extending gate lines laterally over isolation regions to create contact access points, the patent forms contacts vertically through the interlayer dielectric layer directly over the active gate portions. This vertical approach eliminates the need for lateral extensions, maintaining ease of manufacture through self-aligned processes while reducing the standard cell area by eliminating wasted lateral space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces standard cell area by enabling reliable gate contact formation over active regions, eliminating the need for extended gate lines on isolation and reducing layout waste, while maintaining precise alignment without additional lithographic steps.
Implementation Method 1
The gate contact vias are formed by etching through the interlayer dielectric layer, while the trench contact vias are formed by etching through the spin on glass layer. The etch process exhibits selectivity between different dielectric materials, allowing formation of contacts at different depths and locations without additional lithographic steps.
Data Source
Figure 1A~2A
Figure 1B~2B
Figure 1C~2C
AI summary
Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.