Active-Inductor CTLE Equalizer for High-Frequency Boost
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Solution Overview
Problem
SERDES receivers face challenges in compensating for transmission channel attenuation in a power- and area-efficient manner, particularly in high-frequency serial links, due to the need for multiple stages of equalizer core cells, which increase power consumption and silicon area, and non-fixed common-mode output voltage complicates input circuitry design.
Innovation Solution
Employing equalizer filters with active inductors, such as NMOS differential amplifiers and active inductors, to enhance peaking gain and reduce the number of equalizing stages, enabling a two-stage CTLE with fewer stages and lower power consumption, while maintaining a fixed common-mode output voltage for simplified input circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple stages of equalizer core cells are used to compensate for transmission channel attenuation, then the equalization performance is improved, but the power consumption and silicon area increase
Solution Approach 1:
The patent changes the key parameter from passive to active inductors in the equalizer filter circuit. Active inductors provide higher Q-factor and peaking gain, enabling the same equalization performance with fewer stages, thus reducing power consumption while maintaining reliability
Solution Approach 2:
The active inductor serves multiple functions: it provides inductance for frequency compensation, enables peaking gain for high-frequency boost, and reduces the number of stages needed. This multi-functionality allows achieving the same equalization performance with fewer components, thereby reducing power consumption
2Reliability
If multiple stages of equalizer core cells are used to compensate for transmission channel attenuation, then the equalization performance is improved, but the silicon area increases
Solution Approach 1:
The patent changes the key parameter from passive to active inductors in the equalizer filter circuit. Active inductors provide higher Q-factor and peaking gain, enabling the same equalization performance with fewer stages, thus reducing silicon area while maintaining reliability
Solution Approach 2:
The patent extracts and eliminates redundant equalizer stages by using active inductors with higher peaking gain. This removes unnecessary circuit stages that would otherwise be needed to achieve the same high-frequency boost, thereby reducing silicon area
3Adaptability or versatility
If non-fixed common-mode output voltage is used in equalizer core cells, then the circuit design flexibility is increased, but the input circuitry design complexity increases
Solution Approach 1:
The patent applies equipotentiality by maintaining a fixed common-mode output voltage level throughout the equalizer stages. This creates a stable reference potential that simplifies the design of subsequent input circuitry, as they can be designed with fixed biasing requirements rather than having to accommodate varying common-mode levels
Data Source
AI summary
A two-stage continuous-time linear equalizer (CTLE) to increase a peaking gain includes a first stage and a second stage. The first stage comprises a first equalizer core cell and the second stage comprises a second equalizer core cell. The first equalizer core cell and the second equalizer core cell each comprise a differential amplifier comprising a first n-type metal-oxide-semiconductor (NMOS) transistor. The first equalizer core cell and the second equalizer core cell each further comprise an active inductor coupled to the differential amplifier, the active inductor comprising a second NMOS transistor and a load resistor.