Clock-Modulated Active Inductor Circuit for Delay-Power Tradeoff
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Solution Overview
Problem
In high bandwidth applications with high capacitive loads, active inductors improve timing but increase power consumption and voltage headroom, while limiting voltage swing, necessitating a method to control time delay without excess power consumption and voltage degradation.
Innovation Solution
An active inductor modulator circuit with a modulated active inductor and a modulation clock circuit generates a delayed clock signal to enable the inductor prior to signal transitions, using inverters, resistors, capacitors, and switches to control the time delay between input and output signals, and disable the inductor after transitions to reduce power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If active inductors are used to improve timing in high bandwidth applications, then time delay between input and output signals is reduced, but power consumption increases
Solution Approach 1:
The active inductor is modulated using periodic clock signals to enable it only during specific time intervals when timing improvement is needed. The modulation clock circuit generates enable signals that periodically activate the active inductor, allowing it to reduce time delay only during critical signal transitions rather than continuously operating, thereby reducing overall power consumption while maintaining timing benefits when required.
2Loss of time
If active inductors are used to improve timing, then time delay is reduced, but voltage headroom increases
Solution Approach 1:
The active inductor's impedance characteristics are dynamically adjusted through modulation. By controlling the enable signals with modulation clock circuits, the active inductor transitions between active and inactive states, dynamically adapting its behavior to match the timing requirements of different signal transitions. This dynamic operation allows the system to achieve timing improvement only when needed, rather than maintaining fixed high-voltage-headroom operation continuously.
3Loss of time
If the strength of the active inductor is increased to improve timing, then time delay is reduced, but both power and voltage headroom are increased
Solution Approach 1:
The modulation clock circuits generate enable signals in advance of the main clock signal transitions. By anticipating when timing improvement is needed and pre-enabling the active inductor before critical signal edges occur, the system can use a moderately-strength active inductor that provides sufficient timing improvement only during these pre-selected intervals, rather than requiring a continuously-operating high-strength active inductor that would consume excessive power.
Data Source
AI summary
An active inductor modulator circuit is provided. The active inductor modulator circuit may include a circuit to receive an input signal and provide an output signal at an output terminal of the circuit based on a clock signal, a modulated active inductor coupled to the circuit to improve a time delay between the input signal and the provided output signal, and a modulation clock circuit to generate a delayed clock signal to enable the modulated active inductor prior to a transition of the output signal from a first logic state to a second logic state.