Active-Inductor Phase Interpolator for Low-Power High-Bandwidth Clocks
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Solution Overview
Problem
Traditional phase interpolators in integrated circuits face challenges with high power consumption and limited bandwidth, particularly at higher operating frequencies, due to the use of passive resistor loads, which affect the linearity and jitter performance of clock and data recovery systems.
Innovation Solution
The implementation of a phase interpolator using active inductor loads with programmable capacitors and gm-pair segmentation, which provides lower power consumption, higher bandwidth, and improved linearity by introducing frequency peaking and reducing low-frequency noise, while maintaining constant current biasing and digital control over inductance size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If passive resistor load is used in phase interpolator, then circuit simplicity is maintained, but power consumption increases and bandwidth is limited at higher operating frequencies
Solution Approach 1:
The patent changes the load type from passive resistor to active inductor, fundamentally altering the electrical characteristics of the phase interpolator. This parameter change enables frequency peaking that extends bandwidth while reducing power consumption at higher operating frequencies, directly resolving the contradiction between power efficiency and performance
2Speed
If passive resistor load is used in phase interpolator, then implementation is simple, but bandwidth is limited and cannot achieve necessary gain at output CML stage
Solution Approach 1:
The patent transforms the load from a simple resistor to an active inductor circuit, changing the frequency response characteristics. This enables the circuit to achieve the necessary bandwidth and gain at the output CML stage for high-speed operation, directly addressing the bandwidth limitation of resistive loads
Solution Approach 2:
The active inductor acts as an intermediary element that provides frequency peaking and enhances the gain at the output CML stage. This intermediary component enables the phase interpolator to drive high-speed circuits effectively without directly increasing the complexity of the core interpolation logic
3Speed
If higher operating frequencies are targeted, then bandwidth is improved, but power consumption increases to maintain necessary gain
Solution Approach 1:
The patent changes the load type to active inductor, which provides frequency-dependent gain enhancement. This allows the circuit to maintain necessary gain at higher operating frequencies without proportionally increasing power consumption, as the active inductor's frequency peaking effect provides boost where needed
Data Source
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AI summary
A phase interpolator implemented in an integrated circuit to generate a clock signal is described. The phase interpolator comprises a plurality of inputs (121) coupled to receive a plurality of clock signals; a plurality of transistor pairs (330, 332, 340, 342), each transistor pair having a first transistor coupled to a first output node (310) and a second transistor coupled to a second output node (314), wherein a first clock signal associated with the transistor pair is coupled to a gate of the first transistor and an inverted first clock signal associated with the transistor pair is coupled to a gate of the second transistor; a first active inductor load (308) coupled to the first output node; and a second active inductor load (312) coupled to the second output node.