Active Integrator Ramp Generator for Image Sensor ADC Linearity
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Solution Overview
Problem
Existing image sensor circuits face issues with quantization errors and a power/bandwidth tradeoff due to the limitations of current ramp signal generators, particularly in high-resolution applications where increased resolution requires larger circuit areas and higher power consumption or reduced bandwidth.
Innovation Solution
An active integrator generates the ramp signal by charging an integration capacitor with a gain current in the analog domain, eliminating the need for high-resolution digital-to-analog conversion and optimizing power consumption and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-resolution main current mode DAC is used to generate ramp signal, then quantization error is reduced, but circuit area and power consumption increase
Solution Approach 1:
The patent replaces the digital main current mode DAC with an analog integrator circuit that generates the ramp signal by charging a capacitor with a constant current. This substitution of digital-to-analog conversion mechanism with a purely analog integration process eliminates quantization errors inherent in digital conversion while using a simple current source and capacitor instead of a complex high-resolution DAC, thereby reducing both circuit area and power consumption.
2Measurement precision
If high-resolution main current mode DAC is used to generate ramp signal, then quantization error is reduced, but power consumption increases
Solution Approach 1:
The patent replaces the power-intensive digital main current mode DAC with a low-power analog integrator consisting of a constant current source and a capacitor. The analog integration process requires minimal power compared to high-resolution digital-to-analog conversion, thereby eliminating quantization errors while significantly reducing power consumption.
3Measurement precision
If high-resolution main current mode DAC is used to generate ramp signal, then quantization error is reduced, but device complexity increases
Solution Approach 1:
The patent replaces the complex digital main current mode DAC and its control circuitry with a simple analog integrator circuit. The integrator uses a constant current source to charge a capacitor, generating the ramp signal through natural analog integration. This eliminates the need for complex digital control logic, state machines, and high-resolution DAC architecture, thereby reducing device complexity while eliminating quantization errors.
4Speed
If lower resistance is used in ramp signal generation, then bandwidth is improved, but power consumption increases
Solution Approach 1:
The patent changes the fundamental parameter of ramp signal generation from resistive voltage division to capacitive integration. By using a capacitor instead of a resistor, the circuit achieves high bandwidth through the capacitor's ability to respond quickly to current changes, while power consumption is determined only by the constant current source needed to charge the capacitor, not by resistive losses. This parameter change decouples the bandwidth-power tradeoff present in resistive circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces quantization errors, minimizes circuit area, and enhances linearity, resulting in lower power consumption and reduced complexity compared to prior art, while maintaining high resolution and efficient operation.
Implementation Method 1
an active integrator generates the ramp signal by charging an integration capacitor with a gain current in an analog form
Data Source
AI summary
The present invention discloses an image sensor circuit and a ramp signal generator thereof. The image sensor circuit includes: an active pixel sensor (APS) array which includes plural pixel circuits arranged in an array of columns and rows; plural slope analog-to-digital converter (ADC), wherein each of the slope ADC is coupled to the corresponding column, and generates a digital sampling signal according to a ramp signal together with a pixel signal including a reset signal and a image signal which are generated by the pixel circuit located in the selected row and in the column corresponding to the slope ADC; and the ramp signal generator, which generates the ramp signal, wherein the ramp signal generator includes an active integrator, and the active integrator generates the ramp signal by charging an integration capacitor with a gain current.


