Active Interposer Memory for Fast FPGA Sector Reconfiguration
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Solution Overview
Problem
Programmable integrated circuits face challenges in reconfiguration speed and energy consumption, with traditional methods being several orders of magnitude slower than desired and requiring significant silicon real estate and energy for on-chip caching or off-chip fetching of configuration bit streams.
Innovation Solution
An integrated circuit package incorporating an active interposer with memory elements and an auxiliary chip, which includes decryption/decompression circuitry, allows for localized reconfiguration and caching of configuration bit streams, reducing latency and energy consumption by using smart CRAM caches and TSV connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional reconfiguration methods are used to load configuration bit streams, then the programmable device can be reconfigured, but the reconfiguration speed is several orders of magnitude slower than desired
Solution Approach 1:
Configuration bit streams are pre-loaded into buffer memory elements on the interposer before reconfiguration is needed. This preliminary action allows the configuration data to be ready and waiting in close proximity to the programmable device, eliminating the need for slow off-chip fetching during actual reconfiguration events.
Solution Approach 2:
An interposer with buffer memory elements is introduced as an intermediary component between the off-chip storage and the programmable device. This intermediary cache stores configuration data locally, enabling fast retrieval without direct access to slow off-chip storage during reconfiguration operations.
2Speed
If on-chip caching or buffering of configuration bit streams is implemented to hide reconfiguration latency, then reconfiguration speed improves, but silicon real estate cost increases undesirably
Solution Approach 1:
The buffer memory is moved from the two-dimensional plane of the programmable device die to a separate interposer substrate. This dimensional relocation allows the buffer capacity to be significantly increased without consuming valuable silicon real estate on the main device die, as the interposer provides additional memory capacity in a different physical location.
3Adaptability or versatility
If configuration bit streams are fetched repeatedly from off-chip storage, then the programmable device can be reconfigured, but energy consumption increases
Solution Approach 1:
Configuration bit streams are pre-loaded into the interposer buffer memory before reconfiguration events. This preliminary loading action, performed when energy availability is not critical, eliminates the need for repeated high-energy off-chip fetches during actual reconfiguration, thereby reducing energy consumption during operational reconfiguration events.
Solution Approach 2:
The interposer buffer acts as an intermediary energy-efficient storage layer between off-chip storage and the programmable device. Once configuration data is loaded into this intermediate buffer, it can be retrieved multiple times with minimal energy expenditure, avoiding repeated activation of high-energy off-chip storage interfaces.
Data Source
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AI summary
A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.