Comparator-Free Active Isolation Switch for ORing Circuits

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Solution Overview

Problem

Existing ORing circuits in redundant power systems suffer from comparator input offsets affecting FET operation, leading to small output current, reverse current issues, and increased costs due to the necessity of comparators.

Innovation Solution

An active isolation switch comprising a FET, two bi-polar transistors, and an emitter bias resistor, configured to form an inverting amplifier that controls the FET, allowing selective operation between cut-off, active, and saturation regions to prevent current reversal and minimize power dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a comparator is used in the ORing circuit to control the FET, then the isolation function can be achieved, but the comparator input offsets affect the FET control and cause small output current, leading to the FET not opening properly

Engineering Contradiction:
Improveisolation functionVSAvoidoutput current
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent removes the comparator from the circuit entirely and replaces it with a direct transistor-based control mechanism. The FET gate is controlled through a combination of resistors and transistors that directly respond to voltage differences, eliminating the comparator's input offset errors and improving output current precision.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the electronic comparator-based control system with a direct transistor switching mechanism. The control is achieved through voltage-driven transistor operations rather than through a comparator's decision logic, substituting one control paradigm with another that is more precise and offset-free.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Manufacturing precision

If the turn-on threshold of the comparator is moved closer to negative voltage limit to compensate for offset, then the FET can open, but reverse current is fed back to the module from the bus when bus voltage is higher than module voltage

Engineering Contradiction:
Improveturn-on thresholdVSAvoidreverse current
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent introduces an intermediary transistor structure between the FET gate and the voltage sources. This intermediary mechanism (composed of transistors Q1-Q4 and associated resistors) mediates the gate voltage control, enabling precise threshold control without allowing reverse current to affect the module, thus decoupling the threshold adjustment from reverse current issues.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The circuit design proactively prevents reverse current by using the transistor-based control mechanism to maintain proper voltage levels at the FET gate. The control structure anticipates and prevents the conditions that would lead to reverse current flow, rather than reacting to them after they occur.

Inventive Principle:
Principle #9Preliminary anti-action

3Ease of operation

If the comparator is required in the existing ORing circuit to handle voltage comparisons, then the control function is achieved, but the cost of the circuit increases

Engineering Contradiction:
Improvecontrol functionVSAvoidcircuit cost
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent extracts and removes the comparator component from the circuit, replacing its functionality with a simpler transistor-based voltage comparison and control mechanism. This elimination of the expensive comparator component directly reduces circuit cost while maintaining the necessary control function through alternative, more economical means.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the expensive, complex comparator with inexpensive transistor and resistor components that perform the same voltage comparison and control function. The simpler components are more cost-effective and achieve the same operational goals without the overhead of a dedicated comparator IC.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively prevents current reversal and reduces power dissipation by selectively controlling the FET's operating region, enhancing the reliability and efficiency of the power supply system while reducing costs by eliminating the need for comparators.

Implementation Method 1

The first bi-polar transistor may have an emitter connected to the source of the FET and the collector connected to the gate of the FET. The second bi-polar may have a collector connected to the drain of the FET, a base connected to the base of the first bi-polar transistor

Methodology Applied
Scientific EffectTransistor amplification:

Implementation Method 2

When the voltage between the gate and the source of the FET is higher than a threshold voltage, a channel is formed between the source and the drain of the FET, so that a current flows from the source to the drain

Methodology Applied
Scientific EffectField effect transistor conduction:

Implementation Method 3

When the FET is in the cut-off region, a body diode of the FET is equivalent to a forward diode, so that a current does not feedback to an output terminal from an input terminal

Methodology Applied
Scientific EffectDiode conduction: Diode

Data Source

PatentUS9496865B1Active isolation switch
Publication Date: 2016.11.15 COMPUWARE TECH
  • US9496865B1 patent drawing
  • US9496865B1 patent drawing

AI summary

An active isolation switch according to this invention includes a field effect transistor (FET), a first bi-polar transistor and a second bi-polar transistor, and an emitter bias resistor. The FET is formed with a source, a gate, and a drain. The first bi-polar transistor is formed with a first emitter, a first base, and a first collector; the first emitter is connected to the source and the first collector is connected to the gate. The second bi-polar transistor is formed with a second emitter, a second base, and a second collector, the second base is connected to the first base, and the second collector is connected to the drain. The emitter bias resistor is formed with a first terminal and a second terminal; the first terminal is connected to the emitter of the second bi-polar transistor and the second terminal is connected to the emitter of the first bi-polar transistor.The first resistor is connected between a bias voltage and the first collector; the second resistor is connected between the bias voltage and the base of the second bi-polar transistor.