Active LSI Interposer Layout for Higher HBM Bandwidth
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Solution Overview
Problem
Current metal layers in HBM die connections are inadequate for high-powered computing, requiring more space and limiting bandwidth, especially when connecting to SoC dies.
Innovation Solution
Embedding an active local silicon interconnect (LSI) die in an interposer, using organic material, to enhance bandwidth by replacing metal layers with back-end-of-line metal layers and integrating a memory controller, enabling double raw HBM bridges and digital lite I/O.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If metal layers are used for HBM die connections, then the structure is simple and ease of manufacture is improved, but bandwidth is limited and space requirements increase
Solution Approach 1:
An active LSI die is introduced as an intermediary component between the HBM dies and the host die. This LSI die contains memory controller logic and I/O interfaces that actively manage data flow, thereby increasing bandwidth without complicating the overall manufacturing process. The LSI die acts as a mediator that enhances communication capacity while maintaining manufacturing simplicity.
Solution Approach 2:
The patent transitions from passive metal layer connections to an active silicon interconnect dimension. By embedding the LSI die within the interposer structure, the system adds a functional dimension that enables higher bandwidth operations. This dimensional change allows the interposer to actively participate in data transmission rather than merely providing passive electrical connections.
2Productivity
If more HBM dies are connected to increase bandwidth, then bandwidth is improved, but space requirements increase
Solution Approach 1:
The patent combines multiple functions into the active LSI die embedded in the interposer. The LSI die integrates memory controller logic, I/O interfaces, and routing capabilities into a single compact component. This merging allows multiple HBM dies to be connected through a shared active interconnect rather than requiring separate connection structures, thereby increasing bandwidth without proportionally increasing space requirements.
Solution Approach 2:
The active LSI die serves multiple functions simultaneously: it acts as a memory controller, provides I/O interfaces for multiple HBM dies, and enables routing between different dies. This multi-functionality allows a single compact component to support high-bandwidth connections for multiple memory dies without requiring additional space-prohibitive structures for each individual connection.
3Device complexity
If passive interposer structure is used, then device complexity is low, but communication speed is limited
Solution Approach 1:
The active LSI die within the interposer performs self-service by actively managing data flow and communication between HBM dies and the host die. The embedded memory controller logic autonomously handles data routing, timing synchronization, and protocol management without requiring external control circuits, thereby increasing communication speed while maintaining relatively low overall device complexity.
4Productivity
If wide-interface architecture is used for HBM, then bandwidth is improved, but power consumption increases
Solution Approach 1:
The patent replaces power-hungry metal layer interfaces with an active silicon interconnect system. The LSI die uses standard CMOS-based I/O interfaces and routing structures that are more energy-efficient than traditional wide metal interconnects. This substitution maintains high bandwidth capability while reducing power consumption by utilizing the lower-power characteristics of active silicon-based communication pathways.
Data Source
AI summary
A semiconductor module may include an interposer including an active local silicon interconnect (LSI) die, a first semiconductor die on the interposer, and a plurality of second semiconductor dies adjacent the first semiconductor die on the interposer and coupled to the first semiconductor die by the active LSI die. A method of forming a semiconductor module may include attaching an active local silicon interconnect (LSI) die to a carrier substrate, forming a molding material layer around the active LSI die, forming an upper redistribution layer (RDL) structure on the active LSI die and the molding material layer, attaching a first semiconductor die to the upper RDL structure; and attaching a plurality of second semiconductor dies to the upper RDL structure such that the plurality of second semiconductor dies is coupled to the first semiconductor die by the active LSI die.


