Active Material Geometries for HEIP Leakage Reduction
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Solution Overview
Problem
Hot Electron-Induced Punch-through (HEIP) occurs in subwordline drivers (SWDs) of memory devices due to high electrical current, causing current leakage and reducing reliability and performance, which existing techniques partially address through reduced subwordline current, increased oxide thickness, and high breakdown voltage materials, but not effectively in terms of geometries and spacings of active materials.
Innovation Solution
The use of specific geometries and spacings of active materials in transistors, including polysilicon hammerhead materials, notches, and minimum tolerance distances between active materials, to enhance protection against HEIP without significantly increasing chip area costs, thereby reducing HEIP while maintaining array efficiency and cost-effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If reduced subwordline current is used to mitigate HEIP, then HEIP leakage is reduced, but memory access performance deteriorates
Solution Approach 1:
The patent applies different geometries and spacings to different active materials within the same SWD circuit. Specifically, certain active materials are given larger spacings or extended geometries (such as extended active material regions beyond the gate length) to provide localized HEIP protection where most needed, while other active materials use standard spacing to maintain performance. This selective, localized approach allows HEIP mitigation without uniformly degrading memory access performance across the entire circuit.
Solution Approach 2:
The patent extends active materials in the lateral dimension beyond the gate length to create extended active material regions. This dimensional extension provides additional protection against HEIP by increasing the distance over which hot electrons must travel to cause punch-through, without requiring reduction of subwordline current. The extended geometry acts as an additional protective dimension that decouples HEIP protection from performance degradation.
2Object-affected harmful factors
If increased oxide thickness is used to prevent HEIP, then HEIP leakage is reduced, but chip area increases
Solution Approach 1:
The patent changes the geometric parameters of active materials, specifically the spacing between adjacent active materials and the lateral extent of active materials beyond gate lengths. By adjusting these geometric parameters instead of increasing oxide thickness, the patent achieves HEIP protection without proportionally increasing chip area. The extended active material geometries provide HEIP protection through increased lateral dimensions rather than vertical oxide thickness, thereby controlling area overhead.
3Object-affected harmful factors
If high breakdown voltage materials are used to reduce HEIP, then HEIP leakage is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent achieves HEIP protection by changing geometric parameters (spacing and extent) of existing active materials rather than changing material composition to high breakdown voltage materials. This approach maintains compatibility with standard manufacturing processes while achieving HEIP mitigation through carefully designed geometries, thereby avoiding the increased manufacturing complexity that would result from introducing new high breakdown voltage materials.
4Object-affected harmful factors
If extended active material geometries are used to protect against HEIP, then HEIP leakage is reduced, but chip area increases
Solution Approach 1:
The patent extends active materials beyond the gate length, but only to the extent necessary to achieve HEIP protection. The extension is controlled and partial rather than excessive, providing just enough additional protection margin to mitigate HEIP while minimizing the increase in chip area. This balanced approach ensures that the extended geometries provide adequate protection without unnecessarily consuming additional chip real estate.
Data Source
AI summary
Active materials for reducing hot electron-induced punch-through and related apparatuses and computing systems are disclosed. An apparatus includes a first active material, a second active material, a third active material, and a fourth active material. The first active material includes a first outside edge and a first inside edge. The first outside edge defines a first notch. The second active material is spaced at substantially a minimum tolerance distance from the first active material. The third active material is spaced at substantially the minimum tolerance distance from the second active material. The fourth active material includes a second outside edge and a second inside edge. The second inside edge is spaced at substantially the minimum tolerance distance from the third active material. The second outside edge defines a second notch. A computing system includes a memory device including a subwordline driver including the apparatus.