Low Power Active Matrix Display With Alternating Row Scans

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Solution Overview

Problem

Conventional low frame frequency refreshed TFT displays face significant negative stress accumulation, leading to reduced operational lifetime and compromised optical quality, limiting power reduction techniques due to reliability constraints of a-Si:H TFT devices.

Innovation Solution

The display system employs temporal and amplitude modulation of drive waveforms to minimize negative stress accumulation, using an external driver IC and a circuit design that includes two independent row gate signals to prevent charge leakage and extend the operational lifetime at low frame rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If frame refresh rate is reduced from 60Hz to low frame rates (e.g., 1Hz) to reduce power dissipation, then power consumption is significantly reduced, but negative stress accumulation of pixel TFTs occurs much more rapidly degrading display functionality

Engineering Contradiction:
Improvepower consumptionVSAvoidTFT device reliability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies periodic action by implementing a dual-scan mechanism where the display alternates between a first scan pattern (e.g., even rows) and a second scan pattern (e.g., odd rows). This periodic switching prevents continuous negative bias stress accumulation on any single TFT by periodically refreshing different row sets, thereby extending operational lifetime while maintaining low frame rates for power reduction.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent segments the display refresh operation into multiple independent scan patterns. Instead of refreshing all rows simultaneously at high frequency, the display is divided into separate row groups that are refreshed alternately at lower frequencies. This segmentation allows each TFT to experience reduced cumulative stress while the overall display maintains acceptable visual quality.

Inventive Principle:
Principle #1Segmentation

2Duration of action of moving object

If frame refresh rate is reduced to low frame rates to extend battery life, then battery life is extended, but optical quality is compromised with significant flicker

Engineering Contradiction:
Improvebattery lifeVSAvoidoptical quality
Core Design Contradiction:
Duration of action of moving objectVSIllumination intensity

Solution Approach 1:

The patent uses periodic action to alternate between different scan patterns at low frame rates. By switching between first and second scan patterns (e.g., even rows then odd rows), the display maintains acceptable optical quality through periodic updates while keeping average power consumption low, thus extending battery life without severe flicker.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent implements dynamic scanning where the scan pattern adapts between frames - alternating between different row selections. This dynamic approach allows the display to optimize between power consumption and visual quality by varying the refresh strategy rather than using a fixed high-rate refresh, thereby extending battery life while maintaining acceptable optical performance.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP2419894B8Low power active matrix display
Publication Date: 2019.04.03 SES IMAGOTAG SA

AI summary

Described herein are systems and methods for the reduction of power consumption and mitigation of device stress accumulation in low frequency refreshed Liquid Crystal Displays (LCDs). In an exemplary embodiment, two or more transistors in series are used to hold charge on an LCD pixel. To prevent negative stress on the transistors, the transistors are alternately driven to an "on" state so that no one transistor sees a long "off" time. In another embodiment, circuits and signaling waveforms for performing frame writing and stress mitigation are provided that minimize dynamic power consumption and static power consumption in peripheral ESD circuits.