Active Matrix Substrate Back-Gate TFT Moisture Resistance

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Solution Overview

Problem

Oxide semiconductor TFTs in active matrix substrates face challenges with oxygen deficiency and moisture invasion, leading to deteriorated characteristics, particularly in circuit TFTs where slight off-leak currents can cause operation abnormalities, while pixel TFTs can tolerate some threshold voltage shifts.

Innovation Solution

An active matrix substrate design with a specific structure including a first oxide semiconductor TFT in the non-display region and second oxide semiconductor TFTs in the display region, featuring a back-gate structure for circuit TFTs and no back-gate for pixel TFTs, with multiple inorganic and organic insulating layers to control moisture and hydrogen invasion, using silicon nitride and silicon oxide layers for enhanced moisture resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a back-gate electrode is provided in circuit TFT to control threshold voltage, then the controllability of threshold voltage is improved, but the structure complexity increases and moisture resistance deteriorates

Engineering Contradiction:
Improvethreshold voltage controlVSAvoidTFT structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The inorganic insulating layer is designed to serve multiple functions simultaneously: it acts as a gate insulating layer between the gate electrode and oxide semiconductor layer, and as a passivation layer protecting the oxide semiconductor layer from moisture. This multi-functional design eliminates the need for separate protective layers while maintaining threshold voltage control capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The gate insulating layer and passivation layer are merged into a single inorganic insulating layer. This integration simplifies the TFT structure by reducing the number of separate layers, while still providing both electrical insulation for gate control and moisture protection for the oxide semiconductor layer.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If an organic insulating layer is provided between the oxide semiconductor layer and back-gate electrode, then the insulation is improved, but the moisture resistance deteriorates and threshold voltage control is compromised

Engineering Contradiction:
Improveelectrical insulationVSAvoidmoisture invasion
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

An inorganic insulating layer with low moisture permeability is used to create a protective environment around the oxide semiconductor layer. This inert barrier prevents moisture from reaching the oxide semiconductor layer, maintaining its electrical properties and preventing degradation over time.

Inventive Principle:
Principle #39Inert atmosphere (Inert environment)

3Ease of manufacture

If the oxide semiconductor layer is covered with only a first inorganic insulating layer, then the manufacturing simplicity is improved, but the moisture resistance is insufficient causing characteristic deterioration

Engineering Contradiction:
Improvelayer structure simplicityVSAvoidmoisture and hydrogen invasion
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

A composite insulating layer structure is employed, combining a first inorganic insulating layer and a second inorganic insulating layer with different material compositions and properties. This composite structure provides superior moisture and hydrogen barrier properties compared to a single layer, while maintaining manufacturing feasibility through sequential deposition processes.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively suppresses the deterioration of circuit TFT characteristics due to moisture and hydrogen, ensuring reliable operation by controlling the oxide semiconductor layer's properties and preventing depletion states, while maintaining suitable performance for pixel TFTs.

Implementation Method 1

a gate insulating layer covering the lower gate electrode, an oxide semiconductor layer located to face the lower gate electrode with the gate insulating layer being located between the oxide semiconductor layer and the lower gate electrode

Methodology Applied
Scientific EffectOxygen diffusion: Diffusion

Implementation Method 2

featuring a back-gate structure for circuit TFTs and no back-gate for pixel TFTs, with multiple inorganic and organic insulating layers to control moisture and hydrogen invasion, using silicon nitride and silicon oxide layers for enhanced moisture resistance

Methodology Applied
Scientific EffectPhysical barrier: Physical Containment

Data Source

PatentUS10816865B2Active matrix substrate
Publication Date: 2020.10.27 SHARP KK
  • US10816865B2 patent drawing
  • US10816865B2 patent drawing
  • US10816865B2 patent drawing

AI summary

Provided is an active matrix substrate provided with a substrate (1), a peripheral circuit that includes a first oxide semiconductor thin-film transistor (TFT) (101), a plurality of second oxide semiconductor TFTs (102) disposed in a display area, and a first inorganic insulating layer (11) covering the plurality of second oxide semiconductor TFTs (102), the first oxide semiconductor TFT (101) having a lower gate electrode (3A), a gate insulating layer (4), an oxide semiconductor (5A) disposed so as to face the lower gate electrode with the gate insulating layer interposed therebetween, a source electrode (7A) and a drain electrode (8A), and an upper gate electrode (BG) disposed on the oxide semiconductor (5A) with an insulating layer that includes the first inorganic insulating layer (11) interposed therebetween, and furthermore having, on the upper gate electrode (BG), a second inorganic insulating layer (17) covering the first oxide semiconductor TFT (101).