Active Matrix Substrate Gate Electrode Layering for Response Speed
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Solution Overview
Problem
Conventional organic EL display devices with compensation circuits suffer from decreased response speed due to parasitic capacitance, leading to step-like response characteristics and display unevenness, particularly when using analog gray scale driving methods.
Innovation Solution
The active matrix substrate is designed with the gate electrode of the transistor that supplies current to the emissive element positioned in a wiring layer lower than the pixel electrode, reducing parasitic capacitance and eliminating the step-like response by ensuring the gate electrode is covered within a wiring layer closer to the substrate, thereby minimizing capacitance between the gate and pixel electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a compensation circuit is added to compensate for threshold voltage variability, then display uniformity is improved, but parasitic capacitance increases causing step-like response and reduced response speed
Solution Approach 1:
The gate electrode is moved from the same wiring layer as the pixel electrode to a lower wiring layer, utilizing the vertical dimension (layer stacking) to reduce parasitic capacitance while maintaining the compensation circuit functionality. This spatial reconfiguration in the Z-direction resolves the contradiction between maintaining uniformity and improving response speed.
2Ease of manufacture
If the gate electrode is positioned in the same wiring layer as the pixel electrode, then manufacturing is simplified, but parasitic capacitance between gate and pixel electrodes increases
Solution Approach 1:
The solution transitions from a two-dimensional planar arrangement to a three-dimensional stacked arrangement by placing the gate electrode in a lower wiring layer beneath the pixel electrode. This vertical separation reduces parasitic capacitance while maintaining manufacturing feasibility through standard multi-layer wiring processes.
3Stability of the object's composition
If analog gray scale driving is used, then gray scale expression is smooth, but response speed decreases due to parasitic capacitance effects
Solution Approach 1:
By repositioning the gate electrode to a lower wiring layer, the patent reduces parasitic capacitance that degrades response speed in analog gray scale driving, thereby enabling smooth gray scale transitions without the step-like artifacts caused by high capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses the decrease in response speed and prevents step-like response characteristics, enhancing the display performance of organic EL display devices by maintaining high-speed response characteristics and reducing unwanted patterns during screen scrolling.
Implementation Method 1
Parasitic capacitance arises between these members, which are provided in the pixel, and wiring layers, for instance scanning lines, signal lines and the like
Data Source
AI summary
The present invention provides an active matrix substrate driven by an analog gray scale method, and an organic EL display device, in which decrease in response speed of a current emissive element is suppressed. The active matrix substrate of the present invention is driven by an analog gray scale method and is provided with a pixel that has a current emissive element and a transistor that supplies current to the current emissive element. The pixel further has a compensation circuit for compensating variability of threshold voltage in the transistor; the current emissive element has a pixel electrode electrically connected to the transistor; a gate electrode of a transistor that makes up the compensation circuit forms a region covered with the pixel electrode; and a part or the entirety of the gate electrode that is positioned within the region is provided in a wiring layer that is lower than a wiring layer directly below the pixel electrode.