Active Matrix Substrate Top Bottom Gate TFT Hybrid Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing active matrix substrates using oxide semiconductor TFTs face challenges in selectively producing TFTs with characteristics suitable for pixels and peripheral circuits without increasing parasitic capacitance, leading to issues like brightness non-uniformity and increased power consumption, especially in high-definition display devices.
Innovation Solution
The active matrix substrate employs a combination of top gate structure TFTs for peripheral circuits and bottom gate structure TFTs for pixels, with specific layer configurations and insulating layers to reduce parasitic capacitance, including the use of island-shaped insulator and conductor layers to manage resistance and light blocking effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If top gate structure TFTs are used for both pixel TFTs and circuit TFTs, then the current supplying ability is improved, but the parasitic capacitance increases causing signal waveform blunting and brightness non-uniformity
Solution Approach 1:
The invention divides the TFT structure into two types: top gate structure TFTs for circuit regions (where high current supplying ability is needed) and bottom gate structure TFTs for pixel regions (where low parasitic capacitance is critical). This segmentation allows each region to have optimized characteristics without compromising the other.
Solution Approach 2:
Different gate structures are applied to different regions: top gate structure in peripheral circuit regions for high current capability, and bottom gate structure in display pixel regions for low parasitic capacitance. This local differentiation optimizes performance for each specific functional requirement.
2Reliability
If different TFT structures are used for pixel TFTs and circuit TFTs, then the characteristics suitable for each application are achieved, but the manufacturing process becomes complicated
Solution Approach 1:
The invention changes structural parameters (gate electrode position, insulating layer configuration) rather than material parameters, allowing the same oxide semiconductor film to form both top gate and bottom gate TFTs. This reduces manufacturing complexity compared to using different materials or multiple deposition processes.
Solution Approach 2:
The manufacturing process is segmented into regions: top gate structure formation in circuit regions and bottom gate structure formation in pixel regions. This regional segmentation allows different structures to coexist while using a unified base process flow, minimizing overall manufacturing complexity.
3Ease of manufacture
If the same oxide semiconductor film is used for both pixel TFTs and circuit TFTs, then the manufacturing process is simplified, but it becomes difficult to selectively produce TFTs with different characteristics
Solution Approach 1:
Different gate structures (top gate vs. bottom gate) are applied to different regions using the same oxide semiconductor film. This local structural differentiation enables characteristic selectivity (high current for circuits, low capacitance for pixels) while maintaining manufacturing simplicity through unified material processing.
Solution Approach 2:
The invention changes the gate structure parameter (position of gate electrode relative to semiconductor layer) rather than changing the semiconductor material itself. This allows the same oxide semiconductor film to produce TFTs with different electrical characteristics through structural configuration alone.
Data Source
AI summary
An active matrix substrate includes a first TFT of a peripheral circuit and a second TFT arranged in each pixel, wherein: the first TFT is a top gate or double gate TFT that includes an upper gate electrode on a portion of a first oxide semiconductor layer with a gate insulating layer interposed therebetween; the second TFT is a bottom gate TFT that includes a second lower gate electrode arranged on the substrate side of a second oxide semiconductor layer with a lower insulating layer interposed therebetween and includes no gate electrode on the second oxide semiconductor layer; the second TFT including: an island-shaped insulator layer that is arranged on a portion of the second oxide semiconductor layer so as to overlap with at least a portion of the second lower gate electrode, as seen from a direction normal to the substrate; an upper insulating layer that is arranged on the second oxide semiconductor layer and the island-shaped insulator layer; and a source electrode that is arranged on the upper insulating layer, wherein: a portion of the second oxide semiconductor layer that does not overlap with the island-shaped insulator layer is a low resistance region that has a lower specific resistance than a portion thereof that overlaps with the island-shaped insulator layer; and in an intersection between a source bus line and a gate bus line, the lower insulating layer and the upper insulating layer are located between these bus lines.