Active Matrix Substrate Hydrogen Barrier Design
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Solution Overview
Problem
The use of silicon nitride and silicon oxide protection layers in active matrix substrates with oxide semiconductor TFTs leads to deterioration due to hydrogen reduction reactions during annealing, affecting TFT characteristics and increasing production costs due to the need for multiple photolithography steps.
Innovation Solution
Forming a silicon oxide layer on the oxide semiconductor layer without a silicon nitride layer, or forming a silicon oxide layer followed by a silicon nitride layer via a gate electrode, to prevent hydrogen-induced deterioration and reduce the number of masking steps required in the production process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a silicon nitride layer is formed directly on the oxide semiconductor layer as a passivation layer, then the manufacturing process is simplified, but TFT characteristics deteriorate during annealing due to hydrogen reduction reactions in the oxide semiconductor layer
Solution Approach 1:
The passivation layer is divided into two separate layers: a lower passivation layer in contact with the oxide semiconductor layer and an upper passivation layer. This segmentation allows the lower layer to protect the semiconductor while preventing hydrogen from the upper layer from reaching and reducing the oxide semiconductor during annealing, thus resolving the contradiction between manufacturing simplicity and device reliability.
Solution Approach 2:
The lower passivation layer acts as an intermediary barrier between the oxide semiconductor layer and the upper passivation layer. It prevents hydrogen atoms from the silicon nitride-based upper layer from penetrating into and reducing the oxide semiconductor, thereby maintaining TFT characteristics while still providing effective passivation functionality.
2Reliability
If multiple protection layers (silicon oxide and silicon nitride) are formed on the oxide semiconductor layer, then line anticorrosiveness is improved, but the number of photolithography steps increases, reducing production efficiency
Solution Approach 1:
The protection layers are segmented into functionally distinct layers: a lower passivation layer for chemical protection and hydrogen barrier functionality, and an upper passivation layer for mechanical protection and planarization. This segmentation allows each layer to be optimized for its specific function while reducing the total number of processing steps compared to forming multiple layers of the same material.
Solution Approach 2:
Different regions of the device structure receive different protection layer configurations tailored to their specific needs. The lower passivation layer is formed in contact with the oxide semiconductor layer where hydrogen protection is critical, while the upper passivation layer provides general protection for interconnect lines, optimizing both corrosion resistance and production efficiency through localized protection strategies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in active matrix substrates with improved TFT characteristics, enhanced line anticorrosiveness, and increased production efficiency by minimizing the impact of hydrogen and reducing the number of photolithography steps.
Implementation Method 1
TFT characteristics of TFTs with an oxide semiconductor layer in direct contact with a silicon nitride passivation layer may deteriorate during an annealing due to a reduction reaction in the oxide semiconductor layer during the annealing, induced by hydrogen contained in the silicon nitride layer.
Data Source
Figure 1
Figure 2(a)~2(d)
Figure 3(a)~3(d)
AI summary
An active matrix substrate (1) includes a source electrode (32), a drain electrode (33), and a semiconductor layer (31) of oxide semiconductor. A gate insulating layer (42) of silicon oxide is formed on the gate electrode (12a); a source electrode (32), a drain electrode (33), and a semiconductor layer (31) are formed on the gate insulating layer (42); a first protection layer (44) of silicon nitride is formed on the gate insulating layer (42) without covering the semiconductor layer (31); and a second protection layer (46) of silicon oxide is formed on the semiconductor layer (31). The first protection layer (44) covers the signal line (14) and the source connection line (36).