Active Matrix Substrate Multi-Layer Lead-Out Lines Parasitic Capacitance
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Solution Overview
Problem
In display devices, the differences in parasitic capacitance among lead-out lines connected to signal lines cause signal delays, leading to display defects due to varying loads on the signal lines.
Innovation Solution
An active matrix substrate with lead-out lines arranged in at least three layers, where the lead-out lines in the bottommost and topmost layers overlap, and the intermediate layer does not overlap with the other two, reducing parasitic capacitance differences and signal delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If lead-out lines are arranged in three layers with intermediate layer lines adjacent to both bottommost and topmost layer lines, then the number of signal lines can be increased to achieve high-definition display, but parasitic capacitance differences among lead-out lines increase causing signal delays
Solution Approach 1:
The patent transitions from a planar two-dimensional arrangement of lead-out lines to a three-dimensional multi-layer configuration. By stacking lead-out lines across three vertical layers (bottommost, intermediate, and topmost) and utilizing overlapping horizontal arrangements, the design increases the effective routing capacity without proportionally increasing parasitic capacitance differences, thereby enabling high-definition display while maintaining signal integrity.
Solution Approach 2:
The patent applies equipotentiality by forming capacitive coupling between the bottommost and topmost layer lead-out lines through overlapping arrangement. This creates a balanced electrical environment where the intermediate layer lines, which would otherwise experience excessive parasitic capacitance from being adjacent to both outer layers, are electrically compensated. The result is equalized signal propagation characteristics across all lead-out lines regardless of their layer position.
2Adaptability or versatility
If lead-out lines in intermediate layer are adjacent to both bottommost and topmost layer lines with insulating layers interposed, then routing flexibility is improved, but parasitic capacitance on intermediate layer lines increases causing greater signal delays
Solution Approach 1:
The patent introduces an intermediary capacitive coupling mechanism between the bottommost and topmost layer lead-out lines. This intermediary effect serves to electrically balance the intermediate layer lines that would otherwise suffer from excessive parasitic capacitance due to their position adjacent to both outer layers. The overlapping arrangement creates a mediating electrical field that equalizes the potential environment across all layers, allowing the intermediate lines to maintain routing flexibility without suffering from excessive signal delays.
3Area of stationary object
If the frame area is narrowed by separately arranging lead-out lines in three line layers, then display area is maximized, but differences in parasitic capacitance among lead-out lines cause signal delays
Solution Approach 1:
The patent utilizes vertical stacking of lead-out lines across three layers to reduce the horizontal space required for routing. This three-dimensional arrangement allows lead-out lines to be confined within a narrower frame area while still providing sufficient routing capacity for high-definition displays. The overlapping horizontal arrangement of lines across layers further compactes the structure, maximizing the display area without compromising signal integrity through proper capacitive coupling design.
Solution Approach 2:
The patent applies equipotentiality by creating balanced capacitive coupling relationships among all lead-out lines across the three layers. This electrical balancing ensures that despite the compact multi-layer arrangement required to maximize display area, all lead-out lines experience comparable electrical characteristics. The overlapping arrangement between bottommost and topmost layers creates a compensating effect that equalizes parasitic capacitance, preventing signal delays even in the narrowed frame area configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces variations in load on signal lines, minimizing display defects caused by signal delays and improving image quality by equalizing parasitic capacitance across lead-out lines.
Implementation Method 1
a capacitance is formed between the signal line connected with the lead-out line provided in the bottommost line layer, and the signal line connected with the lead-out line provided in the topmost line layer
Data Source
AI summary
Provided is an active matrix substrate in which differences of parasitic capacitances among lead-out lines connected with signal lines can be reduced, as well as a display device and a touch-panel-equipped display device including the same. An active matrix substrate includes: a plurality of signal lines S1 to S9 arranged so as to be parallel to one another in a display area provided on a substrate; and a plurality of lead-out lines L1 to L9 that are connected with the signal lines S1 to S9 outside the display area. Outside the display area, the lead-out lines L1 to L9 are separately arranged in at least three layers, the three layers being a bottommost line layer that is formed at the position closest to the substrate, a topmost line layer that is formed at the position farthest from the substrate, and an intermediate line layer that is formed between the bottommost line layer and the topmost line layer. A capacitance is formed between the signal line S3 connected with the lead-out line L3 provided in the bottommost line layer, and the signal line S4 connected with the lead-out line L4 provided in the topmost line layer.