Active Matrix Substrate Shielding Electrodes for Parasitic Capacitance Reduction
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Solution Overview
Problem
The display quality is reduced in active matrix display devices due to increased parasitic capacitance between detour portions of source lines in the display area, caused by a smaller adjacent interval to minimize the non-display area around openings.
Innovation Solution
An active matrix substrate with a substrate configuration that includes an opening area, an inner non-display area, and a display area, where gate lines and source lines detour around the opening, and pixel electrodes are provided only in the display area. Shielding electrodes are placed in the inner non-display area to overlap with part or all of the source detour portions, reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the adjacent interval between detour portions is made small to reduce the size of the non-display area, then the non-display area size is reduced, but the parasitic capacitance between adjacent detour portions increases
Solution Approach 1:
A shielding electrode is introduced as an intermediary element between adjacent source detour portions. This shielding electrode, positioned in the inner non-display area and overlapping with the detour portions in plan view, acts as an electrostatic shield that reduces the parasitic capacitance between adjacent source lines while allowing the detour portions to be closely spaced for minimizing the non-display area.
Solution Approach 2:
The solution moves from a two-dimensional planar arrangement to a three-dimensional stacked configuration by placing the shielding electrode in a different layer (inner non-display area) that overlaps with the source detour portions. This vertical stacking in the third dimension enables the shielding function without increasing the planar footprint, thus maintaining compact non-display area while reducing parasitic capacitance.
2Object-affected harmful factors
If shielding electrodes are added to reduce parasitic capacitance, then display quality is improved, but device complexity increases
Solution Approach 1:
The shielding electrode is designed to serve multiple functions: it acts as an electrostatic shield to reduce parasitic capacitance between source lines, and simultaneously utilizes the existing inner non-display area space that is already required for other structural purposes. By positioning the shielding electrode in the inner non-display area, the patent makes this space serve the additional function of parasitic capacitance reduction, thereby improving display quality without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves display quality by reducing parasitic capacitance and allows for a smaller non-display area while maintaining the display quality, as the shielding electrodes effectively shield the electric field of the source detour portions.
Implementation Method 1
the display quality may be reduced due to parasitic capacitance between the detour portions and pixel electrodes
Implementation Method 2
shielding electrodes are placed in the inner non-display area to overlap with part or all of the source detour portions, reducing parasitic capacitance
Data Source
AI summary
To reduce a reduction in the quality of a displayed image in portions corresponding to source lines including detour portions in a display area. Gate lines (20) and source lines (30), which intersect with each other, extend on an insulating substrate (1) so as to detour an opening area (A1). Separated portions (24) are provided as lower shielding electrodes (23) in an inner non-display area (A2) so as to be overlapped with source detour portions (31) of the source lines (30) in a plan view.