Active-Matrix Substrate With Source Lines Under Gate Lines
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Solution Overview
Problem
Existing active-matrix substrates for liquid crystal displays face challenges in reducing parasitic capacitance at gate line-source line intersections without increasing wiring resistance or decreasing TFT drivability, especially in larger, high-definition LCDs.
Innovation Solution
The active-matrix substrate design includes a base substrate with source lines under gate lines, separated by a first interlayer insulating film with a lower dielectric constant and greater thickness than the gate insulating film, and electrically connected through contact holes, using a spin-on-glass material with a silica filler to minimize capacitance and prevent cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the line widths are decreased to reduce parasitic capacitance at gate line-source line intersections, then the parasitic capacitance is reduced, but the wiring resistance increases and signal waveforms become rounded
Solution Approach 1:
The patent positions source lines in the third dimension (below gate lines) by forming them on the base substrate before depositing the gate line conductive film. This vertical stacking creates spatial separation between source and gate lines, reducing their overlapping area and thus parasitic capacitance at intersections, while maintaining adequate line widths for low resistance.
Solution Approach 2:
The patent employs a composite interlayer insulating film structure consisting of multiple layers with different dielectric constants. The first interlayer insulating film has a lower dielectric constant than the second, creating a gradient that optimizes capacitance reduction while maintaining electrical performance and signal integrity.
2Object-generated harmful factors
If the insulating film thickness is increased to reduce parasitic capacitance, then the capacitance is reduced, but the drivability of bottom-gate TFTs decreases
Solution Approach 1:
The patent applies different insulating film thicknesses and dielectric constants to different spatial locations and functional regions. The first interlayer insulating film (with lower dielectric constant) is positioned specifically at gate line-source line intersections to reduce parasitic capacitance, while the gate insulating film maintains optimal thickness for TFT drivability. This localized differentiation resolves the contradiction between capacitance reduction and device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitance by over 90% at intersections without affecting wiring resistance or TFT drivability, while also reducing capacitance between source lines and pixel electrodes, thus improving display quality.
Implementation Method 1
a first interlayer insulating film interposed between them, wherein the first interlayer insulating film has a lower dielectric constant and a greater thickness than the gate insulating film
Implementation Method 2
using a spin-on-glass material with a silica filler to minimize capacitance and prevent cracking
Data Source
AI summary
An active-matrix substrate includes: a base substrate; source lines; gate lines; thin-film transistors; and pixel electrodes. Each transistor is a bottom-gate thin-film transistor. The source lines are arranged under the gate lines with a first interlayer insulating film interposed and are electrically connected to the respective source electrodes of their associated thin-film transistors through contact holes cut through the first interlayer insulating film.