Active Matrix Substrate Wiring Connection Structure
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Solution Overview
Problem
The existing top gate structure TFTs in display devices face increased parasitic capacitances at the intersections of gate and source bus lines, leading to a higher load on the source bus line, and the manufacturing process for bottom source structure substrates is challenging due to potential damage to the source metal layer or oxide semiconductor layer when forming wiring line connections.
Innovation Solution
An active matrix substrate with an oxide semiconductor TFT and a wiring line connection section is designed, featuring a bottom source structure where the oxide semiconductor layer is on a lower insulating layer, and a wiring line connection section is formed using a conductive oxide layer with a lower specific resistance than the channel region, reducing parasitic capacitances and protecting the source metal layer during the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a bottom source structure is used to reduce parasitic capacitance, then insulating layer thickness can be increased, but damage may occur to source metal layer or oxide semiconductor layer during wiring line connection formation
Solution Approach 1:
The source electrode is formed in advance, before the wiring line connection section is created. This preliminary formation of the source electrode establishes a reference structure that guides subsequent processing, allowing wiring connections to be formed with proper alignment and minimal damage risk to underlying layers.
Solution Approach 2:
Different regions of the structure are assigned different properties: the source electrode region maintains high conductivity and structural integrity, while the wiring connection region allows for controlled damage or modification during fabrication. This local differentiation enables the wiring connection to be formed without compromising the overall device functionality.
Data Source
AI summary
The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.