Active Matrix TFT Layout With Dual Oxide Layers and Offset Control
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Solution Overview
Problem
Existing active matrix substrates face challenges in fabricating oxide semiconductor TFTs with different characteristics for various applications, as using the same oxide semiconductor film for both pixel and circuit TFTs limits their functional diversity and performance.
Innovation Solution
The active matrix substrate incorporates multiple TFTs with distinct oxide semiconductor layers and gate insulating structures, allowing for independent control of their characteristics by varying the oxide semiconductor materials, gate insulating layer thickness, and offset region lengths to meet specific application requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same oxide semiconductor film is used for both pixel TFTs and circuit TFTs, then manufacturing simplicity is maintained, but functional diversity and performance differentiation are limited
Solution Approach 1:
The patent applies local quality by using different oxide semiconductor films (first oxide semiconductor film for pixel TFTs, second oxide semiconductor film for circuit TFTs) in different regions of the device. This allows each region to have optimized characteristics: pixel TFTs achieve low off-state current while circuit TFTs achieve high mobility, resolving the contradiction between manufacturing simplicity and functional diversity.
2Adaptability or versatility
If different oxide semiconductor films are used for pixel TFTs and circuit TFTs, then functional diversity and performance are enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the oxide semiconductor film formation process into distinct steps: first forming the first oxide semiconductor film for pixel TFTs, then forming the second oxide semiconductor film for circuit TFTs. This segmentation allows independent optimization of each film's properties while maintaining a systematic manufacturing approach, balancing functional diversity with manufacturing complexity.
3Ease of manufacture
If a thick gate insulating layer is used, then manufacturing ease is improved, but current supply performance deteriorates
Solution Approach 1:
The patent applies parameter changes by using a thin gate insulating layer (5 nm to 20 nm thickness) in the top-gate structure. This parameter optimization enables high current supply performance while maintaining manufacturability, as the thin gate insulating layer allows effective gate control and high mobility in the oxide semiconductor channel.
4Manufacturing precision
If offset regions are made longer, then manufacturing precision is improved, but device area increases
Solution Approach 1:
The patent applies asymmetry by making the offset regions asymmetric in design: the source-side offset region and drain-side offset region have different lengths. This asymmetric configuration optimizes the balance between manufacturing precision (controlling TFT characteristics) and device area, allowing precise threshold voltage control without excessive area consumption.
Data Source
AI summary
An active matrix substrate includes a first TFT having an oxide semiconductor layer formed from a first oxide semiconductor film and a second TFT having an oxide semiconductor layer formed from a second oxide semiconductor film. The oxide semiconductor layer of each TFT includes a high-resistance region including a channel region and offset regions and low-resistance regions including a source contact region, a drain contact region, and interposed regions. The first TFT has a gate insulating layer including a first insulating film and a second insulating film. The second TFT has a gate insulating layer including the second insulating film but not including the first insulating film. A total length L1 of the offset regions of the first TFT in a channel length direction is greater than a total length L2 of the offset regions of the second TFT in the channel length direction.