Active Memory Data Compression Processing Elements
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Solution Overview
Problem
The processing speed of computer systems using active memory devices is limited by the time required to transfer operand data to and from the active memory, which is similar to passive memory devices, necessitating a more efficient data transfer method between active memory devices and external systems.
Innovation Solution
An integrated circuit active memory device with an array of processing elements, such as SIMD or MIMD processors, compresses and decompresses data through a host/memory interface port, enhancing data bandwidth by executing compression and decompression algorithms stored in program memory, thereby increasing data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred uncompressed between host and memory device, then data transfer simplicity is maintained, but data bandwidth and transfer efficiency are limited
Solution Approach 1:
Data is compressed before being written to memory, and decompressed before being read from memory. This preliminary compression/decompression action reduces the volume of data transferred through the host/memory interface, thereby increasing effective data bandwidth without requiring a wider physical interface.
Solution Approach 2:
Processing elements act as intermediaries between the host interface and the memory array. These PEs perform compression and decompression operations, mediating the data transfer process to reduce the amount of data that must be transmitted through the external interface while maintaining data integrity and accessibility.
2Speed
If uncompressed data is processed, then processing simplicity is maintained, but data bandwidth and processing speed are limited
Solution Approach 1:
The processing architecture is divided into multiple processing elements (PEs), each capable of independently performing compression, decompression, and data processing operations. This segmentation allows parallel processing of multiple data streams simultaneously, significantly increasing overall processing speed while distributing the computational complexity across multiple simpler units.
Solution Approach 2:
Processing elements are designed to perform multiple functions including compression, decompression, data processing, and memory control. This multi-functionality reduces the need for separate dedicated hardware for each operation, increasing processing speed while managing overall device complexity through versatile, reusable computational units.
Data Source
AI summary
An integrated circuit active memory device receives task commands from a component in a host computer system that may include the active memory device. The host system includes a memory controller coupling the active memory device to a host CPU and a mass storage device. The active memory device includes a command engine issuing instructions responsive to the task commands to either an array control unit or a DRAM control unit. The instructions provided to the DRAM control unit cause data to be written to or read from a DRAM and coupled to or from either the processing elements or a host/memory interface. The processing elements execute instructions provided by the array control unit to decompress data written to the DRAM through the host/memory interface and compress data read from the DRAM through the host/memory interface.