Active Memory Gather Scatter Processing Element
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Solution Overview
Problem
Computer systems face significant memory latency and access time delays due to long data access times when communicating between the main processor and memory devices, especially when addressing non-contiguous memory locations requires address translation.
Innovation Solution
An active memory device with a processing element that can autonomously execute instructions for gathering and scattering data across multiple memory locations, reducing latency by performing operations within the memory device itself, using a load store queue, instruction buffer, and decoder to handle gather and scatter instructions, and translating virtual addresses to real addresses for efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data is accessed from non-contiguous memory locations, then data can be retrieved from required positions, but memory access time and latency increase significantly
Solution Approach 1:
The patent segments the memory access operation into multiple phases: fetching base address, calculating individual element addresses, and retrieving data elements. By breaking down the non-contiguous access into manageable segments, the system can optimize each phase separately and reduce overall access time while maintaining the capability to retrieve scattered data elements efficiently.
Solution Approach 2:
The patent performs preliminary address calculation and preparation before actual data retrieval. The base address is fetched first, and address offsets are pre-calculated based on the scatter pattern requirements. This preliminary action allows the subsequent data retrieval to proceed more quickly without repeated address translation overhead.
2Adaptability or versatility
If address translation is performed for each memory access, then virtual addresses can be mapped to physical addresses, but access latency increases
Solution Approach 1:
The patent merges multiple address translation operations into a single batch operation. Instead of performing address translation for each individual memory access, the system consolidates the translation of multiple virtual addresses to physical addresses in one unified process, significantly reducing the time overhead while maintaining full address mapping functionality.
Solution Approach 2:
The patent implements a universal address translation mechanism that handles both contiguous and non-contiguous memory accesses through a single integrated system. The same address translation infrastructure serves multiple purposes: base address translation, element address calculation, and scatter/gather operations, eliminating the need for separate translation paths and reducing overall latency.
3Quantity of substance
If data is transferred between processor and memory over long distances, then large amounts of data can be accessed, but energy consumption increases
Solution Approach 1:
The patent applies local quality by implementing scatter and gather operations that enable data to be processed closer to where it is stored in memory. By allowing the processor to efficiently access and manipulate data elements at their specific memory locations without requiring extensive data movement, the system reduces the distance data needs to travel and minimizes energy consumption while maintaining large data access capacity.
4Ease of operation
If multiple cache levels are traversed for memory access, then data can be retrieved from different cache hierarchies, but access time increases
Solution Approach 1:
The patent extracts the address translation and address calculation functions from the main processor execution path and implements them directly in the memory subsystem. By taking out these time-consuming operations from the processor-cache-memory path, the system eliminates unnecessary cache traversal steps while maintaining the flexibility to access data from different cache hierarchies, thereby reducing access time without sacrificing retrieval flexibility.
Data Source
AI summary
Embodiments relate to loading and storing of data. An aspect includes a method for transferring data in an active memory device that includes memory and a processing element. An instruction is fetched and decoded for execution by the processing element. Based on determining that the instruction is a gather instruction, the processing element determines a plurality of source addresses in the memory from which to gather data elements and a destination address in the memory. One or more gathered data elements are transferred from the source addresses to contiguous locations in the memory starting at the destination address. Based on determining that the instruction is a scatter instruction, a source address in the memory from which to read data elements at contiguous locations and one or more destination addresses in the memory to store the data elements at non-contiguous locations are determined, and the data elements are transferred.