Active Message Handler Compilation in Heterogeneous Systems

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Solution Overview

Problem

Heterogeneous system architectures, such as multicore systems with different processing cores and unified memory, pose challenges for flexible and efficient active message enablement, particularly in improving network performance and programmability across diverse compute resources.

Innovation Solution

The method involves receiving active messages in a heterogeneous system and compiling intermediate language message handlers into machine instruction set architecture (ISA) code for execution on selected execution units, allowing for flexible compilation, scheduling, and efficient utilization of heterogeneous compute resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If active messages are used in heterogeneous systems to exploit diverse compute resources, then parallelism and network performance are improved, but device complexity and scheduling difficulty increase

Engineering Contradiction:
Improvenetwork performanceVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a universal message handler interface that can execute on multiple types of heterogeneous processors (CPUs, GPUs, FPGAs). The message handler is designed with a standardized structure that accepts diverse compute resources, allowing the same active message framework to exploit parallelism across different processor types without requiring separate handling logic for each architecture.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces an intermediate representation (IR) layer that acts as a mediator between the high-level active message specification and the diverse underlying hardware architectures. This IR serves as a common intermediate format that can be translated to multiple target architectures, simplifying the scheduling and execution management across heterogeneous systems by providing a unified interface layer.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If message handlers are precompiled for specific architectures, then execution speed is improved, but adaptability to different processors is reduced

Engineering Contradiction:
Improveexecution speedVSAvoidprocessor compatibility
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The patent segments the compilation process into distinct stages: high-level message handler specification, intermediate representation generation, and target architecture-specific code generation. This segmentation allows the message handler logic to be separated from architecture-specific optimizations, enabling the same high-level specification to be efficiently compiled for multiple different processor types through the intermediate representation layer.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs parameterized message handler templates that can be instantiated with different architectural parameters. The intermediate representation includes placeholders and parameters that are resolved during code generation for the target architecture, allowing the same logical message handler to be adapted to different processors by changing compilation parameters rather than rewriting the handler logic.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If dynamic compilation of message handlers is implemented, then flexibility and programmability are improved, but compilation time and overhead increase

Engineering Contradiction:
ImproveprogrammabilityVSAvoidcompilation time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent performs preliminary compilation of message handlers to an intermediate representation at program load time or during an initialization phase, before the active messages are actually executed. This preliminary action converts the high-level message handler specifications into optimized IR form in advance, so that during runtime, only lightweight architecture-specific code generation is needed, significantly reducing the compilation overhead during actual message execution.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10025605B2Message handler compiling and scheduling in heterogeneous system architectures
Publication Date: 2018.07.17 ADVANCED MICRO DEVICES INC
  • US10025605B2 patent drawing
  • US10025605B2 patent drawing
  • US10025605B2 patent drawing

AI summary

A receiving node in a computer system that includes a plurality of types of execution units receives an active message from a sending node. The receiving node compiles an intermediate language message handler corresponding to the active message into a machine instruction set architecture (ISA) message handler and the receiver executes the ISA message handler on a selected one of the execution units. If the active message handler is not available at the receiver, the sender sends an intermediate language version of the message handler to the receiving node. The execution unit selected to execute the message handler is chosen based on a field in the active message or on runtime criteria in the receiving system.