Active Net Parasitic Extraction for Circuit Simulation
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Solution Overview
Problem
Current memory characterization methods using instance-based approaches face impractical run times and large memory footprints due to high extraction and simulation times, making them unsuitable for practical application despite their accuracy.
Innovation Solution
The method identifies active nets in a circuit design through simulation, extracts a parasitic netlist from a limited part of the circuit determined by these active nets, and performs simulation using tools like HSIM and Star-RC, reducing the netlist size and simulation time while maintaining accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If instance-based approach with completely extracted netlist is used for memory characterization, then accuracy is improved, but extraction run time and simulation run time become prohibitively high
Solution Approach 1:
The patent extracts only the parasitic netlist corresponding to active nets from the complete circuit netlist, rather than extracting the entire netlist. This selective extraction reduces the size of the netlist that needs to be processed during simulation, thereby reducing extraction run time while maintaining characterization accuracy for the critical active portions of the circuit
Solution Approach 2:
The patent segments the complete circuit netlist into active nets and inactive nets based on simulation results. By identifying and separating the active portion of the circuit that actually contributes to the output signal, the method focuses computational resources on the relevant segments, reducing overall processing time while preserving accuracy
2Measurement precision
If instance-based approach with completely extracted netlist is used for memory characterization, then accuracy is improved, but memory footprint becomes prohibitively large
Solution Approach 1:
The patent extracts only the parasitic netlist corresponding to active nets from the complete circuit netlist, rather than extracting the entire netlist. This selective extraction reduces the size of the netlist that needs to be processed during simulation, thereby reducing extraction run time while maintaining characterization accuracy for the critical active portions of the circuit
Solution Approach 2:
The patent segments the complete circuit netlist into active nets and inactive nets based on simulation results. By identifying and separating the active portion of the circuit that actually contributes to the output signal, the method focuses computational resources on the relevant segments, reducing overall processing time while preserving accuracy
3Measurement precision
If complete netlist simulation is performed for circuit characterization, then accuracy is improved, but simulation run time becomes prohibitively high
Solution Approach 1:
The patent performs a preliminary simulation to identify active nets before the main characterization simulation. This preliminary action determines which nets are actually contributing to the output signal, allowing the subsequent extraction and simulation steps to focus only on the relevant active portion of the circuit, thereby reducing overall simulation run time while maintaining accuracy
Solution Approach 2:
The patent extracts only the parasitic netlist corresponding to active nets from the complete circuit netlist, rather than extracting the entire netlist. This selective extraction reduces the size of the netlist that needs to be processed during simulation, thereby reducing extraction run time while maintaining characterization accuracy for the critical active portions of the circuit
Data Source
AI summary
A computer system identifies active nets in a netlist of a circuit design by performing simulation of the netlist. Active nets are interconnections between circuit components showing a level of activity during the simulation. The computer system extracts, from a layout of the circuit design, a parasitic netlist of a part of the circuit design, where the part determined by the active nets. The parasitic netlist is a list of parasitic nets, or unwanted circuit interconnections that are unavoidable adjuncts of the active nets. The computer system performs simulation of the circuit design including the netlist of a circuit design and the parasitic netlist of the part of the circuit design.