Active N-Well Switching for PMOS Power Switch Latch-Up Control
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Solution Overview
Problem
Existing solutions for eliminating latch-up effects and minimizing channel resistance in MOS transistors are challenging due to difficulties in efficiently biasing the n-well regions of PMOS devices, particularly in systems with separate power supplies, leading to issues like leakage, latch-up, forward-biased parasitic diodes, floating outputs, and excessive voltage drops.
Innovation Solution
An active n-well voltage switching circuit that remaps two independent voltage supplies to maximize their difference, using a comparator and level shifters to bias the n-well of PMOS power switches, ensuring all parasitic diodes remain reverse biased and minimizing back-gate effects without requiring special fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the n-well is permanently connected to the highest system voltage to prevent parasitic diode conduction, then latch-up prevention is improved, but the ON resistance of the PMOS device significantly increases due to reverse body bias
Solution Approach 1:
The patent applies dynamic n-well biasing by switching the n-well connection between the highest voltage supply and the local source voltage based on the conduction state of the PMOS device. When the PMOS is ON, the n-well is connected to the source voltage to minimize body effect and channel resistance. When the PMOS is OFF, the n-well is connected to the highest voltage supply to prevent parasitic diode conduction and latch-up. This dynamic switching resolves the contradiction between latch-up prevention and low channel resistance.
2Reliability
If the n-well is connected to the highest system voltage, then parasitic diode conduction is prevented, but the circuit area must be increased to compensate for higher resistance
Solution Approach 1:
The dynamic n-well biasing circuit allows the use of minimum-length PMOS devices by switching the n-well connection to minimize body effect during conduction. This eliminates the need to increase device area to compensate for resistance, as the body effect is dynamically minimized when the PMOS is ON, allowing standard minimum-length devices to achieve the required performance without area penalty.
3Reliability
If the n-well is permanently biased at the highest voltage, then latch-up is prevented, but design time and cost increase due to larger device areas
Solution Approach 1:
The dynamic n-well biasing circuit enables the use of minimum-length PMOS devices by switching the n-well connection to minimize body effect during conduction. This reduces the required device area and accelerates design turnaround, as designers no longer need to oversized devices to compensate for resistance penalties. The added switching circuitry is minimal compared to the area savings achieved.
4Object-affected harmful factors
If the n-well is connected to local source voltage during conduction, then channel resistance is minimized, but parasitic diodes may become forward-biased causing latch-up
Solution Approach 1:
The patent implements dynamic switching of the n-well bias voltage based on the conduction state. During conduction, the n-well is connected to the source voltage to minimize body effect and channel resistance. During non-conduction, the n-well is connected to the highest voltage supply to ensure all parasitic diodes are reverse-biased and prevent latch-up. The switching control logic ensures the appropriate connection is made based on the PMOS gate voltage state, resolving the contradiction between low resistance and latch-up prevention.
Data Source
AI summary
An n-well voltage switching circuit (60) and methodology are disclosed for generating a maximum bias voltage (VMAX) at the output voltage node with cross-coupled PMOS switching transistors (63) connected to a voltage supply remapping circuit (61, 62, 64) which receives first and second power supplies (VSUP1, VSUP2) and generates first and second gate driving signals (G1, G4), wherein the first and second gate driving signals are connected, respectively, to the gates of the first and second cross-coupled PMOS transistors (P5, P6) to pull a gate for one of the cross-coupled PMOS transistors to ground so that the higher of the first and second power supplies is coupled to the output voltage node over one of the first and second cross-coupled PMOS transistors, thereby generating a maximum bias voltage at the output voltage node.