Per-Chip Active ODT for High-Speed Memory Signal Integrity
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Solution Overview
Problem
Existing On Die Termination (ODT) technologies in high-speed memory modules are limited by fixed passive terminations that result in inefficient power usage and suboptimal signal quality due to inability to select different termination values for each memory chip, leading to timing skew and signal quality issues.
Innovation Solution
Implementing an on-die active termination circuit with a termination value register and setting circuit that allows each memory device to select a unique impedance value from a plurality of options for the data I/O bus, enabling dynamic impedance adjustment for improved signal quality and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed passive termination is used, then signal reflection is prevented, but power consumption increases and signal quality deteriorates due to inability to adjust termination values
Solution Approach 1:
The patent implements dynamic termination by replacing fixed passive resistors with active termination circuits on each memory device that can dynamically adjust their impedance values based on their position on the data bus. Each memory device includes a termination circuit with controllable impedance that can be programmed to different values (e.g., 20, 40, 60, or 80 ohms) to optimize signal quality while minimizing power consumption across different locations on the bus.
Solution Approach 2:
The patent changes the impedance parameter of termination circuits from fixed to variable values. By allowing each memory device to select different termination impedance values based on its physical position and signal characteristics, the system optimizes both signal quality and power efficiency. The termination value register and setting circuit enable precise control of these impedance parameters for each device.
2Reliability
If fixed passive termination is used, then implementation is simple, but signal quality is suboptimal due to timing skew across different memory locations
Solution Approach 1:
The patent segments the termination function by implementing individual termination circuits within each memory device rather than using a single shared passive termination. This allows each memory device to independently control its own termination characteristics, enabling precise compensation for timing skew and signal quality issues specific to each device's location on the data bus.
Solution Approach 2:
The patent applies local quality by allowing each memory device to have customized termination impedance values tailored to its specific position and signal characteristics on the data bus. Instead of a uniform termination approach, each device can optimize its termination parameters locally, with devices at different positions using different impedance values to compensate for varying signal path lengths and timing skew.
3Use of energy by moving object
If mode-selected ODT is used, then power efficiency improves, but effectiveness is limited by single termination value across all devices
Solution Approach 1:
The patent extends mode-selected ODT from a single global termination mode to dynamic per-device termination control. Each memory device independently selects and adjusts its own termination impedance value based on its specific requirements, transforming the static mode selection into a dynamic, device-specific parameter that can be optimized for each location on the data bus.
Solution Approach 2:
The patent expands the parameter selection capability from a single termination value for all devices to multiple selectable impedance values for each individual device. The termination value register and setting circuit enable each memory device to choose from different impedance parameters (e.g., 20, 40, 60, or 80 ohms), providing versatile adaptation to different signal conditions while maintaining power efficiency.
Data Source
AI summary
A memory device is coupled to a subset of lines of a data input/output (I/O) bus. The memory device includes an on-die active termination circuit for terminating the subset of lines of the data I/O bus with a selected impedance being one of a plurality of selectable impedances; a termination value register being coupled to the on-die active termination circuit for storing a value representing the selected impedance; and a termination value setting circuit being coupled to the termination value register, for setting the value representing the selected impedance in the termination value register.