Bottom-Gate Active Pattern Layout for Source/Drain Connectivity
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Solution Overview
Problem
There is a growing demand for semiconductor devices with high reliability and integration density, which existing technologies have not adequately addressed in terms of structural complexity and integration density.
Innovation Solution
A semiconductor device design featuring a channel region between source/drain patterns with a gate electrode on the bottom surface and an upper interconnection line on the insulating layer, along with specific configurations of source/drain patterns and active regions to enhance connectivity and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the structural complexity and integration density are increased to satisfy high reliability and performance requirements, then the device performance and reliability are improved, but the manufacturing complexity and process difficulty increase
Solution Approach 1:
The source/drain structure is segmented into multiple portions (first source/drain portion, second source/drain portion) with different widths. This segmentation allows each portion to be optimized independently for its specific function, improving overall device reliability while managing structural complexity through functional decomposition
Solution Approach 2:
Different portions of the source/drain structure are given different local qualities - specifically different widths at different locations. The first portion has a larger width for robust connection, while the second portion has a smaller width for precise alignment, allowing each region to have optimal properties for its specific role in the device
2Adaptability or versatility
If the integration density is increased to achieve higher functionality, then the device capability is improved, but the manufacturing precision requirements become more stringent
Solution Approach 1:
The gate electrode is formed to extend beyond the active pattern boundaries in advance, creating overlapping regions before the source/drain structures are formed. This preliminary action establishes alignment references that guide subsequent processing steps, ensuring precise positioning of source/drain structures relative to the gate electrode, thereby improving manufacturing precision for high-density integration
3Area of stationary object
If the source/drain patterns are spaced closer to increase integration density, then the device compactness is improved, but the channel region connectivity becomes more difficult to maintain
Solution Approach 1:
The gate electrode is nested within the source/drain structure configuration, with the gate extending beyond the active pattern to create overlapping regions. This nesting arrangement allows the gate to serve dual functions as both the control element and as a structural bridge that maintains channel connectivity even when source/drain patterns are closely spaced, thereby maintaining reliability while improving compactness
Data Source
AI summary
A semiconductor device includes an active pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source/drain pattern.