Multiplexing Output Stage Using Active Peaking to Reduce ISI Jitter
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Solution Overview
Problem
The increasing data rate requirements, particularly for 100 Gbps and 112 Gbps, are hindered by large jitter noise induced by intersymbol interference (ISI) effects, which distort signals and reduce communication reliability.
Innovation Solution
A multiplexing circuit with an impedance circuit between the gate terminal of a first type transistor and the output terminal, utilizing N-type and P-type MOS transistors, and an equivalent impedance that peaks in high frequency bands to minimize ISI effects, facilitating higher bandwidth capabilities without the use of physical passive inductors, thus reducing chip area and enabling IC integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If physical passive inductors are used to achieve high frequency peaking, then bandwidth capability is improved, but chip area increases and IC integration becomes difficult
Solution Approach 1:
The patent replaces physical passive inductors (mechanical/electrical components) with an active impedance circuit composed of MOS transistors and capacitors. This substitution eliminates the need for large-area inductors while achieving the same high-frequency peaking effect through active circuitry, thereby maintaining bandwidth capability without increasing chip area.
Solution Approach 2:
The patent changes the impedance characteristics dynamically using MOS transistor operating states. By adjusting the operating point and parameters of the MOS transistors in the impedance circuit, the circuit achieves frequency-dependent impedance peaking that mimics the effect of physical inductors, but with much smaller area footprint suitable for IC integration.
2Productivity
If data rate is increased to meet higher bandwidth requirements, then productivity is improved, but intersymbol interference effects increase causing larger jitter noise
Solution Approach 1:
The patent applies preliminary anti-action by using the impedance circuit to pre-compensate for intersymbol interference effects before they degrade the signal. The frequency-peaking characteristic of the impedance circuit proactively counteracts the low-pass filtering effect of the transmission line, preventing ISI-induced jitter noise from developing, thereby maintaining signal quality at high data rates.
3Area of stationary object
If impedance circuit uses MOS transistors instead of passive inductors, then device complexity increases, but chip area is reduced
Solution Approach 1:
The impedance circuit uses MOS transistors that serve multiple functions: they provide the frequency-peaking impedance effect, act as active inductors, and can be integrated with other circuit blocks. This multi-functionality reduces the need for separate discrete inductor components and simplifies the overall circuit architecture despite the active nature of the impedance circuit.
Data Source
AI summary
A multiplexing circuit including an output terminal, a first type transistor, a second type transistor and an impedance circuit; the first type transistor is coupled to the output terminal, wherein a gate terminal of the first type transistor is configured to receive a control signal and free from receiving a clock signal; the second type transistor is coupled to the output terminal, wherein a gate terminal of the second type transistor is configured to receive the clock signal, and the first type transistor is different from the second type transistor; the impedance circuit is arranged to provide an impedance between the gate terminal of the first type transistor and the output terminal, wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor.