Active Pillar Fine Pattern Geometry for High-Aspect-Ratio Etching

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Solution Overview

Problem

In semiconductor integrated circuit devices, the formation of fine patterns with high aspect ratios leads to changes in electrical characteristics due to varying etching gas availability, affecting the width and height of patterns, particularly in conductive layers and active pillars, which complicates the achievement of high integration density and efficient electrical performance.

Innovation Solution

The semiconductor integrated circuit device incorporates a target fine pattern and an adjacent fine pattern with specific width and length gradients, where the width decreases and length increases towards the lower region, allowing for self-organization without additional masks or etching processes, thereby maintaining the volume and area of the pattern and improving electrical characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a fine pattern with high aspect ratio is formed, then integration density is improved, but etching gas availability decreases in lower regions causing width variation

Engineering Contradiction:
Improveintegration densityVSAvoidpattern width uniformity
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent applies asymmetry by designing the fine pattern with a non-uniform width profile where the width varies along the height direction. Specifically, the pattern has a wider upper region and a narrower lower region, which compensates for the reduced etching gas availability in lower regions during the etching process. This asymmetric geometry allows the pattern to maintain electrical characteristics while achieving high aspect ratio for improved integration density.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent changes the geometric parameters of the fine pattern by making the width a function of height position. The width parameter is deliberately varied along the vertical direction to compensate for etching process non-uniformities. This parameter change approach allows the pattern to achieve both high aspect ratio and controlled electrical characteristics despite the challenging etching conditions in high aspect ratio structures.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If additional masks or etching processes are used to maintain pattern dimensions, then manufacturing precision is improved, but fabrication complexity and time increase

Engineering Contradiction:
Improvepattern dimension controlVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies self-service by designing the fine pattern geometry to automatically compensate for etching process variations. The asymmetric width profile is built into the pattern design itself, allowing it to self-correct for the reduced etching gas availability in lower regions without requiring additional masks or etching steps. This self-compensating design simplifies the fabrication process while maintaining pattern dimension control.

Inventive Principle:
Principle #25Self-service

3Reliability

If pattern width is maintained constant, then electrical characteristics are improved, but aspect ratio cannot be increased for high integration density

Engineering Contradiction:
Improveelectrical characteristicsVSAvoidintegration density
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent resolves this contradiction by making the pattern width asymmetric along the height direction. The width is not constant but varies systematically, being wider in the upper region and narrower in the lower region. This asymmetric design allows the pattern to achieve high aspect ratio for improved integration density while the wider upper region maintains sufficient electrical characteristics.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS20240381619A1Semiconductor integrated circuit device and method of manufacturing the same
Publication Date: 2024.11.14 SK HYNIX INC
  • US20240381619A1 patent drawing
  • US20240381619A1 patent drawing
  • US20240381619A1 patent drawing

AI summary

A semiconductor integrated circuit device may include a target fine pattern and an adjacent fine pattern. The target fine pattern may have a first width, a first length and a first height. The first width may be gradually decreased toward a lower region. The first length may be gradually increased toward the lower region. The first height may be greater than the first width and the first length. The adjacent fine pattern may have contact with the target fine pattern along a lengthwise direction. The adjacent fine pattern may have a second width, a second length and the first height. The second width may be gradually decreased toward the lower region. The second length may be gradually decreased toward the lower region.