Active Pillar Channel Doping Layout for Lower GIDL Leakage
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Solution Overview
Problem
The gate-induced drain leakage (GIDL) current in semiconductor structures, particularly in ultra-deep submicron transistor devices, is a significant factor affecting reliability and power consumption, exacerbated by the inevitable overlapping area between the gate and drain during doping processes, leading to increased band-to-band tunneling currents.
Innovation Solution
A semiconductor structure with a counter-doped region in the channel region, forming a PN junction and reducing the effective width of the channel region to obstruct the GIDL current, combined with a gate-all-around design to enhance current control and increase integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the gate and drain have an overlapping area during doping process to reduce contact resistance, then contact resistance is reduced, but GIDL current increases
Solution Approach 1:
The channel region is segmented into multiple doped regions with different doping types and concentrations. By dividing the channel into distinct zones (first doped region, second doped region, third doped region), the patent creates a structured doping profile that reduces GIDL current while maintaining low contact resistance through the optimized distribution of dopant regions
Solution Approach 2:
Different regions of the channel are assigned different doping characteristics (type and concentration). The first doped region has a first doping type, the second doped region has a second doping type, and the third doped region has a third doping type with concentration higher than the other two. This local differentiation allows optimization of each region's function to simultaneously reduce contact resistance and GIDL current
2Productivity
If the transistor device size is shrunk to increase integration density, then integration density is improved, but GIDL current becomes more serious
Solution Approach 1:
The patent introduces a vertical dimension to the doping structure by creating multiple doped regions at different positions along the channel length. This multi-layered doping approach (first, second, and third doped regions with different characteristics) adds dimensional complexity to control GIDL current while enabling smaller device footprints through efficient space utilization
Solution Approach 2:
The patent systematically changes doping parameters (type and concentration) across different channel regions. By varying the doping type (first, second, third doping types) and concentration (third region has higher concentration), the patent optimizes device performance to reduce GIDL current while maintaining small device dimensions for high integration density
3Reliability
If the gate dielectric layer becomes thinner to improve device performance, then device performance is improved, but GIDL tunneling current increases sharply
Solution Approach 1:
The patent implements preliminary doping actions by creating specific doped regions (first, second, and third doped regions with different types and concentrations) in the channel before final device operation. This pre-structured doping profile prepares the device to handle thin gate dielectric conditions by establishing electric field distributions that suppress GIDL tunneling current while maintaining performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces GIDL current by minimizing the overlapping area and electric field intensity, improving the reliability and usability of the semiconductor structure while maintaining high integration density.
Implementation Method 1
electrons in the substrate near the interface of the gate-drain overlapping area undergo band-to-band tunneling (BTBT) between a valence band and a conduction band to generate a current, which is called GIDL tunneling current
Data Source
AI summary
Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: an active pillar, where the active pillar includes: a channel region, as well as a first doped region and a second doped region located at two sides of the channel region, the channel region, the first doped region, and the second doped region having a same doping type, where a counter-doped region is arranged in the channel region, the counter-doped region is close to the first doped region, and a doping type of the counter-doped region is different from a doping type of the channel region; and a gate, where the gate surrounds a part of the channel region, and in a plane in which an axis of the active pillar is located, projection of the gate partially overlaps with projection of the counter-doped region.