Active Pillar Grain Size Control for 3D Memory Capacity
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Solution Overview
Problem
Current three-dimensional integrated circuit (3D-IC) memory techniques face limitations in increasing memory capacity, with fine pattern and multi-level cell methods being expensive and limited in bit density, respectively.
Innovation Solution
A semiconductor device structure featuring a stack structure with an active pillar that penetrates sub-stack structures, where the doping concentration of crystallization-inducing metal varies along the pillar's height, and a metal-induced lateral crystallization method is used to increase the grain size of poly-silicon in the active pillar, improving cell current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine pattern technique is used to increase memory capacity, then memory capacity is improved, but manufacturing cost increases
Solution Approach 1:
The patent changes the physical and chemical parameters of the active pillar by introducing crystallization-inducing metal doping with varying concentrations at different heights, and controlling grain size through thermal processing, to improve cell current and memory capacity without requiring expensive fine pattern techniques
Solution Approach 2:
The active pillar is constructed as a composite material system containing poly-silicon with embedded crystallization-inducing metal atoms (such as aluminum, gallium, or indium), creating a multi-component structure that achieves enhanced electrical properties and memory performance through material composition rather than complex patterning
2Quantity of substance
If multi-level cell (MLC) technique is used to increase memory capacity, then memory capacity is improved, but bit density per cell is limited
Solution Approach 1:
The patent achieves higher bit density per cell by changing the electrical parameters of the memory cell through controlled variation of crystallization-inducing metal doping concentration at different heights of the active pillar, and by controlling the grain size of poly-silicon, enabling multiple stable states within a single cell structure
3Reliability
If doping concentration of crystallization inducing metal is increased in the active pillar, then grain size increases and cell current improves, but doping uniformity becomes difficult to control
Solution Approach 1:
The patent applies local quality by varying the doping concentration of crystallization-inducing metal at different heights of the active pillar, with higher concentrations at the bottom and lower concentrations at the top, optimizing grain growth and cell current locally rather than using uniform doping throughout
Solution Approach 2:
The patent performs preliminary action by pre-doping the active pillar with crystallization-inducing metal atoms before the main crystallization process, and using thermal processing to trigger controlled grain growth, thereby achieving desired grain size and electrical properties through staged processing rather than single-step doping
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach enhances memory capacity by improving cell current through controlled doping and grain size increase, addressing the limitations of existing 3D-IC memory techniques.
Implementation Method 1
increasing a grain size of the active pillar by a metal induced lateral crystallization method
Implementation Method 2
performing an annealing process to diffuse the crystallization inducing metal into the active pillar
Implementation Method 3
performing an annealing process to diffuse the crystallization inducing metal into the active pillar
Data Source
AI summary
The inventive concepts provide semiconductor devices and methods of fabricating the same. According to the method, sub-stack structures having a predetermined height and active holes are repeatedly stacked. Thus, cell dispersion may be improved, and various errors such as a not-open error caused in an etching process may be prevented. A grain size of an active pillar used as channels may be increased or maximized using a metal induced lateral crystallization method, so that a cell current may be improved. A formation position of a metal silicide layer including a crystallization inducing metal may be controlled such that a concentration grade of the crystallization inducing metal may be controlled depending on a position within the active pillar.