Active Capacitive Shielding in PLA Circuits for Crosstalk Control
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Solution Overview
Problem
Parasitic capacitive couplings in programmable logic arrays (PLAs) cause misfunction by making adjacent lines incorrectly appear decoded, and existing passive shielding solutions increase area or reduce input/output capacity.
Innovation Solution
Implement active capacitive shields on one side of product term straps in the AND plane and output lines in the OR plane, dynamically driven to offset capacitive coupling by switching voltage in the opposite direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If passive shields are placed between each line in the AND plane and between each output line in the OR plane, then capacitive coupling effects are reduced, but the area occupied by shields increases
Solution Approach 1:
The patent transforms static passive shields into dynamic active shields that are driven by clock signals. The shields switch between voltage states in synchronization with the logic operations, actively compensating for capacitive coupling effects only when needed during dynamic transitions, thereby reducing the required shield area while maintaining effectiveness.
Solution Approach 2:
The invention changes the voltage state of shields dynamically based on operational requirements. By controlling shield voltage levels through clock-driven switching, the system adapts shield behavior to match the timing of logic transitions, reducing capacitive coupling interference without requiring continuous high-voltage shielding across the entire device area.
2Object-affected harmful factors
If passive shields are placed between each line in the AND plane and between each output line in the OR plane, then capacitive coupling effects are reduced, but the number of inputs, product terms, and outputs that can be provided for the same area is reduced
Solution Approach 1:
By making shields dynamic and clock-driven, the invention enables more compact spacing between logic lines. The active shielding only activates during critical transition periods, allowing reduced spacing between functional elements and thereby increasing the density of inputs, product terms, and outputs that can be packed into the same area.
Solution Approach 2:
The patent combines the shielding function with the existing clock distribution infrastructure. By using clock signals to drive shields, the system merges two functions (clocking and shielding) into a unified approach, eliminating the need for separate dedicated shield control circuits and freeing up area for additional logic elements.
3Object-affected harmful factors
If passive shields are placed on both sides of each product term line and output, then capacitive coupling effects are minimized, but the device complexity increases
Solution Approach 1:
The invention simplifies shield configuration by using a single dynamic shield per logic line instead of multiple passive shields on both sides. The clock-driven approach allows one actively controlled shield to compensate for coupling from adjacent lines, reducing the total number of shield structures and their interconnections while maintaining protection against capacitive interference.
Solution Approach 2:
The dynamic shields are self-regulating through their clock-driven operation. The shielding effect automatically activates and deactivates in sync with logic transitions without requiring external control circuits or complex configuration, thereby reducing overall device complexity while maintaining effective capacitive coupling mitigation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces capacitive coupling effects while minimizing area usage and maintaining functionality, allowing for more inputs/outputs without increasing PLA size.
Implementation Method 1
The dense metallic interconnects inside the AND and OR planes (which include the codings of the AND and OR planes and the output lines of the OR plane) create parasitic capacitive couplings that may cause misfunction in the dynamic operation of the PLA.
Data Source
AI summary
In accordance with various embodiments of the present disclosure, a programmable logic array circuit is provided. In some embodiments, the programmable logic array circuit comprises an AND plane comprising a plurality of groups of product term straps, an OR plane comprising a plurality of output lines, a first plurality of dynamically driven shield lines in the AND plane, and a second plurality of dynamically driven shield lines in the OR plane. Each of the plurality of groups of product term straps is adjacent to only one corresponding one of the first plurality of dynamically driven shield lines. Each of the plurality of output lines is adjacent to only one corresponding one of the second plurality of dynamically driven shield lines.