Active Pull-Up Circuit for Level Shifter Reliability
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Solution Overview
Problem
Level-shifter circuits face reliability issues due to high voltage capability requirements and reduced headroom, leading to unintended behavior and faulty operation when the overdrive voltage of NMOS devices exceeds that of PMOS devices, especially in scenarios with large supply range differences.
Innovation Solution
The enhanced active pull-up circuit employs two parallel pull-up paths with P-type transistors and control circuitry to ensure robust operation by maintaining a strong source-gate overdrive voltage, independent of the supply headroom, using a current-mirror structure and a pull-up resistor to effectively pull-up intermediate nodes and change logic states across different voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional active pull-up circuit with a single PMOS transistor is used, then the circuit structure is simple, but the reliability deteriorates when the overdrive voltage of NMOS devices exceeds that of PMOS devices, leading to unintended behavior and faulty operation
Solution Approach 1:
The pull-up function is segmented into two parallel paths: one PMOS transistor (first pull-up path) and another PMOS transistor (second pull-up path), each handling different voltage conditions. This segmentation ensures that at least one path remains reliable under varying supply headroom conditions, resolving the reliability issue without excessive complexity.
Solution Approach 2:
The control circuitry proactively adjusts the gate voltage of the second PMOS transistor based on the intermediate node voltage before the input voltage transitions. This preliminary action ensures the second pull-up path is prepared to activate when needed, preventing faulty operation and maintaining reliability across supply range differences.
2Adaptability or versatility
If the supply headroom is reduced to increase voltage domain flexibility, then the adaptability improves, but the reliability deteriorates due to insufficient overdrive voltage for PMOS devices
Solution Approach 1:
The circuit dynamically adapts the pull-up strength by activating different paths based on supply conditions. The control circuitry monitors the intermediate node voltage and adjusts the second PMOS transistor's gate voltage accordingly, ensuring adequate overdrive voltage is maintained even when supply headroom is reduced, thus preserving reliability while maintaining voltage domain flexibility.
Solution Approach 2:
The gate voltage of the second PMOS transistor is changed as a control parameter based on the intermediate node voltage. This parameter change allows the transistor to operate with sufficient overdrive voltage even when the supply headroom is reduced, resolving the contradiction between adaptability and reliability.
3Ease of operation
If a single pull-up path is used to maintain simple circuit operation, then the ease of operation is improved, but the propagation delay increases under reduced supply headroom conditions
Solution Approach 1:
The pull-up function is divided into two parallel paths with different characteristics. The first path handles normal conditions while the second path provides enhanced pull-up strength when needed, reducing propagation delay under reduced supply headroom without significantly complicating the overall circuit operation.
Solution Approach 2:
The second pull-up path provides excessive pull-up strength relative to the first path, ensuring that the intermediate node is pulled up quickly even under reduced supply headroom. This partial redundancy resolves the propagation delay issue while keeping the circuit relatively simple.
Data Source
AI summary
An active pull-up circuit which is operated between an upper voltage and a lower voltage and which pulls up an intermediate node to the upper voltage in reaction to an input voltage of the pull-up circuit falling from the upper voltage to an intermediate voltage is described. The pull-up circuit comprises a first transistor having a source terminal coupled to the upper voltage, a drain terminal coupled to the intermediate node and a gate terminal coupled to the input voltage. The pull-up circuit comprises a second transistor having a source terminal coupled to the upper voltage, a drain terminal coupled to the intermediate node and a gate terminal coupled to a control node. In addition, the pull-up circuit comprises control circuitry configured to pull the control node to a voltage level of the intermediate node, subject to the input voltage falling from the upper voltage to the intermediate voltage.