Transient Active Pull-Up I2C for Faster Bus Rise Time
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Solution Overview
Problem
Existing I2C-bus compatible devices face a trade-off between increasing bus speed and reducing average power consumption, as faster speeds require lower resistance pull-up resistors, which increase power demand.
Innovation Solution
The implementation of a transient active pull-up I2C (TAP-I2C) module using high side driver transistors to precharge I2C bus capacitances during logic level transitions, allowing for faster bus transfer operations while reducing the need for external pull-up resistors and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If lower resistance pull-up resistors are used to increase bus speed, then bus transfer speed is improved, but average power consumption increases
Solution Approach 1:
The patent applies preliminary action by precharging the bus lines before data transfer operations. The pull-up resistors are activated in advance to charge the capacitance of the SDA and SCL lines, so that when actual data transfer occurs, the lines are already charged and ready for rapid switching. This eliminates the need for continuously strong pull-up resistors during normal operation, thereby reducing average power consumption while maintaining fast bus transfer speeds.
Solution Approach 2:
The patent implements periodic action by using pulsed pull-up resistors that are activated only during specific periods when needed for bus line charging. Instead of maintaining continuous strong pull-up resistance, the system uses periodic pulses to charge the bus lines, followed by periods where weaker or disabled pull-up resistors reduce power consumption. This periodic activation pattern resolves the contradiction between speed and power by providing strong pull-up only when necessary.
2Speed
If stronger pull-up resistors (lower resistance) are used to charge bus lines faster, then bus speed is improved, but power demand increases
Solution Approach 1:
The patent applies preliminary action by precharging the bus lines before data transfer operations. The pull-up resistors are activated in advance to charge the capacitance of the SDA and SCL lines, so that when actual data transfer occurs, the lines are already charged and ready for rapid switching. This eliminates the need for continuously strong pull-up resistors during normal operation, thereby reducing average power consumption while maintaining fast bus transfer speeds.
Solution Approach 2:
The patent changes the resistance parameter dynamically by using variable resistance pull-up circuits that can switch between different resistance states. During precharge operations, the resistance is lowered to enable fast charging of the bus lines. During normal idle or data transfer operations, the resistance is increased or the pull-up is disabled, reducing power demand. This dynamic parameter change resolves the contradiction between charging speed and power demand.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables I2C bus speeds of up to 5-10 MHz while reducing power consumption by using higher resistance pull-up resistors only for maintaining logic levels, rather than charging bus capacitance, thus balancing speed and power efficiency.
Implementation Method 1
precharge the capacitance of the SDA line and then precharge the capacitance of the SCL line during low to high logic level transitions
Data Source
AI summary
An I2C-bus compatible device when functioning as a clock master comprises a transient active pull-up I2C (“TAP-I2C”) logic module having high side driver transistors, e.g., P-channel field effect transistors (FETs), coupled between a positive supply voltage and respective serial data (“SDA”) and serial clock (“SCL”) lines on the I2C bus. The high side output driver transistors for the SDA and SCL lines are sequentially pulsed on by the TAP I2C logic module for brief periods to first precharge the capacitance of the SDA line and then precharge the capacitance of the SCL line during low to high logic level transitions thereof. Precharging the capacitances of the I2C bus lines will also accelerate bus transfer operations for all I2C compatible devices since the capacitances of the I2C bus lines will be charged much faster through the low impedance active pull-up driver transistors then through the passive pull-up resistors.