Active Pull-Up Level Shifting for CMOS-to-I2C Signal Translation

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Solution Overview

Problem

Existing circuits fail to provide both active pull-up and logic translation functions on a single bus, particularly from CMOS to I2C signal modes, which is necessary for applications like HDMI where high-capacitance cables are expensive and limit cable length.

Innovation Solution

An integrated circuit with an active pull-up and logic translation capability that dynamically shifts signal levels from CMOS to I2C mode, minimizing transition state duration, using a combination of impedance control, pull-up, and pull-down circuits to manage signal transitions and maintain signal mode levels across different capacitance loads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional circuits are used for level shifting from CMOS to I2C signal mode, then signal mode translation is achieved, but transition state duration is excessive and signal integrity is compromised

Engineering Contradiction:
Improvesignal mode translation accuracyVSAvoidtransition state duration
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent implements dynamic level shifting by detecting the input signal state (high, low, or transition) and dynamically adjusting the output signal level. When a transition is detected on the input bus, the circuit dynamically switches between different output levels (VDD_I2C or ground) to minimize the duration of the transition state on the output bus, thereby resolving the contradiction between accurate signal translation and minimized transition duration.

Inventive Principle:
Principle #15Dynamics

2Ease of manufacture

If higher capacitance cables are used to reduce cost, then cable cost decreases, but signal integrity and protocol compliance deteriorate

Engineering Contradiction:
Improvecable costVSAvoidsignal integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent employs feedback mechanisms where the circuit continuously monitors the input bus state and uses this information to control the output bus. The feedback loop detects transition states and triggers appropriate pull-up or pull-down actions to maintain signal integrity even with higher capacitance cables, thereby allowing cost reduction without sacrificing reliability.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The circuit changes operational parameters dynamically by switching between different output voltage levels (VDD_I2C or ground) based on the detected input state. This parameter change capability allows the system to compensate for the effects of higher cable capacitance, maintaining signal integrity while enabling the use of lower-cost cables.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If cable length is extended to 100 feet to increase flexibility, then installation flexibility improves, but signal transition compliance with I2C protocol deteriorates

Engineering Contradiction:
Improveinstallation flexibilityVSAvoidI2C protocol risetime compliance
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent implements preliminary action by proactively detecting transition states on the input bus before they propagate through the cable. When a transition is detected, the circuit preemptively switches the output bus to the appropriate state, compensating for the delayed signal propagation in long cables. This preliminary action ensures I2C protocol compliance even with extended cable lengths up to 100 feet.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7446565B2Apparatus and method that provides active pull-up and logic translation from one signal mode to another signal mode
Publication Date: 2008.11.04 SEMICON COMPONENTS IND LLC
  • US7446565B2 patent drawing
  • US7446565B2 patent drawing
  • US7446565B2 patent drawing

AI summary

Described is an integrated circuit that causes an input signal having one signal mode with a high state, a low state and a transition state to be dynamically level shifted to another signal mode with a respective high and low state, while minimizing a duration of the transition state of the output signal, wherein the one signal mode and the another signal mode have respectively different high and low state levels.