Active Region Necking Profile for Residue-Free Source/Drain Etching
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Solution Overview
Problem
Current source/drain etching techniques in multigate devices, such as gate-all-around (GAA) devices, leave behind semiconductor residue, leading to weak points and increased complexity in IC manufacturing.
Innovation Solution
A method involving alternating etching processes with specific etchant gases and parameters to create a necking profile in the active region, ensuring complete etching of the source/drain regions without residue, using a combination of chlorine-containing and fluoride-containing gases to achieve selective etching in different directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If current source/drain etching techniques are used in multigate devices, then etching speed is improved, but semiconductor residue is left behind causing weak points in the source/drain region
Solution Approach 1:
The etching process is divided into multiple alternating steps using different etchants (chlorine-containing and fluoride-containing gases) with different selectivities. Each etching step is followed by a deposition step, creating a segmented sequence that progressively removes material while maintaining control. This segmentation allows complete removal of semiconductor material without leaving residue that would compromise source/drain region integrity.
Solution Approach 2:
The patent changes etching parameters by alternating between different etchant chemistries (chlorine-based and fluoride-based gases) with different etch rates and selectivities. By varying the etching parameters across multiple steps and adjusting deposition thicknesses, the process achieves complete material removal while maintaining precise control over the trench profile and avoiding residue formation.
2Manufacturing precision
If alternating etching and deposition processes are used to create necking profile, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The manufacturing process is segmented into alternating etching and deposition cycles, where each cycle creates a portion of the desired necking profile. By dividing the profile formation into discrete steps with alternating material removal and deposition, the process achieves precise control over the active region geometry while maintaining a systematic approach that can be automated.
Solution Approach 2:
The patent employs periodic alternation between etching and deposition operations to progressively shape the active region. This periodic action allows the process to build the complex necking profile through repeated cycles of material removal and addition, with each cycle contributing to the final precise geometry while following a predictable, repeatable pattern.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The necking profile allows for improved etching efficiency, reducing the risk of residue and enhancing the integrity of the source/drain regions, thereby improving the manufacturing process and device performance.
Implementation Method 1
performing a first etch process with a first etchant and a first etch duration, wherein the first etchant includes a chlorine-containing chemical
Implementation Method 2
performing a second etch process with a second etchant and a second etch duration, wherein the second etchant includes a fluoride-containing chemical
Implementation Method 3
epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.