Active Region Array Patterning Beyond Lithography Limits

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Solution Overview

Problem

The existing methods for forming active region arrays in semiconductor structures, such as DRAM, are limited by the precision of lithography, restricting the further reduction of active region size and hence the arrangement density.

Innovation Solution

A method involving self-aligned double patterning (SADP) is employed, where multiple mask layers are sequentially formed and etched to create intricate patterns on the substrate, allowing for the formation of smaller active regions and increased density by overcoming lithography precision limitations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If single-pattern or LELE is used to form active region array, then the process is simpler, but the active region size cannot be further reduced due to lithography precision limitations

Engineering Contradiction:
Improveactive region sizeVSAvoidpatterning process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patterning process is segmented into multiple distinct steps: forming the first mask layer with initial patterns, depositing the second mask layer, creating the third mask layer with additional patterns, and performing sequential etching operations. This segmentation allows each step to contribute to the final high-precision active region pattern, overcoming the resolution limits of single-step lithography while maintaining manageable process complexity through systematic division of tasks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from two-dimensional planar patterning to three-dimensional multi-layer mask structuring. By stacking multiple mask layers (first mask layer, second mask layer, third mask layer) at different vertical levels and using flank structures covering sidewalls, the process creates patterns in the vertical dimension that translate to enhanced horizontal resolution, effectively bypassing lithography precision constraints through dimensional extension.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If active region size is reduced to improve arrangement density, then the arrangement density increases, but the lithography process precision becomes insufficient

Engineering Contradiction:
Improvearrangement density of active regionsVSAvoidlithography process precision
Core Design Contradiction:
Quantity of substanceVSMeasurement precision

Solution Approach 1:

The methodology performs preliminary patterning actions by forming the first mask layer with initial patterns before subsequent processing steps. The flank structures are formed in advance to define precise etching boundaries, and the multiple mask layers are prepared sequentially with predetermined patterns. This preliminary structuring establishes a framework that guides subsequent etching operations to achieve the final high-density active region arrangement with precision beyond conventional lithography capabilities.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Multiple mask layers serve as intermediary structures between the lithography process and the final active region pattern. The first mask layer, second mask layer, and third mask layer act as sequential intermediaries that transfer and refine patterns at each stage. These intermediary mask structures enable the decoupling of lithography resolution from final pattern dimensions, allowing high arrangement density to be achieved through cumulative pattern refinement across multiple intermediary layers rather than relying solely on single-step lithography precision.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11887859B2Method for forming active region array and semiconductor structure
Publication Date: 2024.01.30 CHANGXIN MEMORY TECH INC
  • US11887859B2 patent drawing
  • US11887859B2 patent drawing
  • US11887859B2 patent drawing

AI summary

A method for forming an active region array and a semiconductor structure are provided. The method for forming the active region array includes the steps of: providing a substrate; forming a first mask layer on a surface of the substrate, a first etched pattern being provided in the first mask layer; forming a second mask layer covering a surface of the first mask layer; forming a third mask layer having a second etched pattern on a surface of the second mask layer; forming a flank covering a sidewall of the second etched pattern; removing the third mask layer to form a third etched pattern between adjacent flanks; etching the first mask layer along the third etched pattern to form a fourth etched pattern in the first mask layer; and etching the substrate along the first etched pattern and the fourth etched pattern, to form multiple active regions in the substrate.