Continuous Active Region Layout With Tie Gate Isolation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The miniaturization of semiconductor processes leads to yield degradation and reliability issues in integrated circuits due to local layout effects and layout-dependent effects, which affect the electrical characteristics of semiconductor devices.

Innovation Solution

The integrated circuit design includes a continuous active region with tie gate electrodes and source/drain regions, along with tie gate contacts and source/drain contacts, where the tie gate contacts are shorted to the source/drain contacts, enhancing electrical isolation and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If gate spacing and gate length are miniaturized to achieve smaller device size, then device density increases, but local layout effects and layout-dependent effects worsen, causing yield and reliability degradation

Engineering Contradiction:
Improvegate lengthVSAvoidcircuit reliability
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

An isolation gate electrode is introduced as an intermediary element between adjacent active gate electrodes. This isolation gate acts as a mediator to shield the channel region from local layout effects caused by proximity to other circuit features, thereby maintaining device reliability despite miniaturization of gate dimensions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate structure is segmented into active gate electrodes for device operation and an isolation gate electrode for mitigating layout effects. This segmentation allows the isolation gate to be positioned specifically between active gates to counteract local layout effects without interfering with the normal operation of adjacent devices.

Inventive Principle:
Principle #1Segmentation

2Reliability

If isolation gate electrode is provided in gate tie-down manner to mitigate local layout effects, then device reliability improves, but device structure and circuit complexity increase

Engineering Contradiction:
Improvedevice reliabilityVSAvoidgate electrode structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The isolation gate electrode is designed to perform multiple functions: it serves as an isolation element to mitigate local layout effects, acts as a tie-down structure to control threshold voltage, and functions as part of the overall gate electrode system. This multi-functionality reduces the need for separate dedicated structures, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12230684B2Integrated circuit with continuous active region and raised source/drain region
Publication Date: 2025.02.18 SAMSUNG ELECTRONICS CO LTD
  • US12230684B2 patent drawing
  • US12230684B2 patent drawing
  • US12230684B2 patent drawing

AI summary

According to example embodiments, an integrated circuit includes a continuous active region extending in a first direction, a tie gate electrode extending in a second direction crossing the first direction on the continuous active region, a source/drain region provided adjacent the tie gate electrode, a tie gate contact extending in a third direction perpendicular to the first direction and the second direction on the continuous active region and connected to the tie gate electrode, a source/drain contact extending in the third direction and connected to the source/drain region, and a wiring pattern connected to each of the tie gate contact and the source/drain contact and extending in a horizontal direction. A positive supply power is applied to the wiring pattern.