Active Reset Circuit for CMOS Image Sensor Noise Reduction

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Solution Overview

Problem

CMOS image sensors face challenges with reset noise, which leads to variations in reset levels among pixels, reducing the dynamic range and image quality, especially under high analog gain conditions, as the variation in reset signal is magnified and limits the range available for the light-dependent portion of the pixel signal.

Innovation Solution

The implementation of an active reset circuit with a first and second current path, where the selection transistor and first transistor are ON to set the potential of the charge storage node based on the gate potential of a second transistor, reducing reset level variation by stabilizing the voltage on the floating diffusion node, thereby enhancing the dynamic range of the image sensor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If high analog gain is used to amplify the pixel signal, then the signal-to-noise ratio is improved, but the reset signal variation is magnified and limits the dynamic range

Engineering Contradiction:
Improvesignal-to-noise ratioVSAvoiddynamic range
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent applies preliminary action by performing reset of the floating diffusion node before the light-dependent signal accumulation. The reset circuit actively sets the potential of the floating diffusion node to a predetermined level prior to exposure, ensuring that reset level variations are minimized before signal accumulation begins. This preliminary reset action prevents reset variations from being magnified by subsequent high analog gain amplification.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs parameter changes by dynamically adjusting the reset voltage level applied to the floating diffusion node. The reset circuit modifies the electrical parameters (voltage potential) of the floating diffusion node based on detected reset level variations, thereby compensating for reset noise and enabling high analog gain operation without dynamic range limitation.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If reset voltage is changed dynamically to minimize reset spread, then reset noise is reduced, but the circuit complexity increases

Engineering Contradiction:
Improvereset noiseVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary reset circuit that mediates between the power supply and the floating diffusion node. This reset circuit includes a reset transistor and associated control logic that acts as an intermediary mechanism to dynamically adjust the reset voltage level, reducing reset noise while adding controlled complexity only where needed for reset management.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements feedback by monitoring the reset level variations and using this information to adjust the reset voltage dynamically. The reset circuit receives feedback about the actual reset level and modifies its output accordingly, creating a closed-loop system that minimizes reset spread while maintaining manageable circuit complexity through intelligent control.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10659714B2Image sensor and electronic device with active reset circuit, and method of operating the same
Publication Date: 2020.05.19 SONY GROUP CORP
  • US10659714B2 patent drawing
  • US10659714B2 patent drawing
  • US10659714B2 patent drawing

AI summary

An image sensor including a pixel circuit and an active reset circuit. The pixel circuit includes a light sensing element, a storage node selectively connected to the light sensing element, an output transistor configured to, during a readout operation, output a signal that is based on a potential of the charge storage node to an output line, and a selection transistor that controls the readout operation. The active reset circuit includes a first current path and a second current path, the first current path extending from a power supply node to the output line via the selection transistor and the output transistor, and the second current path extending from the power supply node to the output line via a first transistor and a second transistor. The active reset circuit is configured to, when the selection transistor and the first transistor are both ON, set a potential of the charge storage node based on a potential of a gate of the second transistor.