Active Resistor Array Layout for Smaller Memory Chips
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Solution Overview
Problem
The existing semiconductor memory devices have a significant area occupancy by analog circuits, particularly the active resistor arrays used in voltage dividers, which hinders the reduction of chip size and integration density.
Innovation Solution
The implementation of an active resistor array with a specific layout structure that includes a first and second active resistor region with an isolation element layer in between, and selection transistors connected to these regions, allowing for a reduced chip size and improved circuit characteristics by optimizing the layout pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the active resistor array is implemented with a conventional repeated layout pattern, then the circuit functionality is achieved, but the chip size area is increased
Solution Approach 1:
The patent merges the first and second active resistor regions by removing the isolation element layer between adjacent active resistors, allowing them to be physically combined into a single continuous region. This merging reduces the total chip area occupied by the active resistor array while maintaining the electrical functionality of having separate selectable resistor groups.
Solution Approach 2:
The patent reorganizes the layout from a conventional linear repetition pattern to a multi-dimensional arrangement where active resistors are distributed across first and second regions in different spatial directions. The gate layer extends across both regions to provide unified control, creating a two-dimensional optimization that reduces area compared to one-dimensional linear repetition.
2Area of stationary object
If the isolation element layer is placed between all active resistors, then the electrical isolation is achieved, but the chip size area is increased
Solution Approach 1:
The patent applies local quality by selectively placing the isolation element layer only between active resistors that require electrical isolation for separate selection groups, rather than between all adjacent active resistors. This localized isolation approach maintains the necessary electrical separation for independent group selection while minimizing the total area consumed by isolation structures.
Solution Approach 2:
The patent segments the active resistor array into distinct first and second regions that can be independently selected by separate transistors. The isolation element layer is strategically placed to create these functional segments only where needed, allowing the majority of adjacent resistors to share common contacts and reduce area without compromising the ability to independently select different resistor groups.
Data Source
AI summary
An active resistor array of a semiconductor memory device comprises a first active resistor in a first active resistor region; a second active resistor in the first active resistor region and arranged in parallel with the first active resistor, and an isolation element layer interposed therebetween; a third active resistor formed in a second active resistor region; a first selection transistor formed in a first selection transistor region and connected to the second active resistor; and a second selection transistor formed in a second selection transistor region and connected to the third active resistor. The first and second selection transistors are connected to the same gate layer. The gate layer of the first and second selection transistors is on the isolation element layer. Since example embodiments may help to ensure the uniformity of the layout pattern, active resistance distribution may be improved due to reduction in process variation.