Active Silicon Bridge for Short-Channel ASIC D2D Links
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Solution Overview
Problem
Conventional die-to-die (D2D) interfaces in integrated circuits face challenges with high bandwidth requirements, long channel lengths, and complex signal equalization techniques like FIR, CTLE, and DFE, which are not feasible at early process development stages, leading to design complexity and delayed market entry.
Innovation Solution
The implementation of an active silicon bridge with reduced channel length to micrometers, utilizing a purely digital CMOS interface and active microelectronic devices, eliminating the need for complex equalization techniques, and enabling high-bandwidth communication through parallel connections and flip-flops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional D2D interfaces use long channel lengths to connect ASICs, then bandwidth requirements can be met through high bit rates per wire, but signal attenuation and intersymbol interference increase, requiring complex equalization techniques (FIR, CTLE, DFE) that add design complexity, power consumption, and area
Solution Approach 1:
The patent changes the critical parameter of channel length from millimeters to micrometers by using a through-silicon via (TSV) architecture. This parameter change fundamentally alters the signal propagation characteristics, reducing attenuation and intersymbol interference to levels that do not require complex equalization techniques, thus resolving the contradiction between signal quality and design complexity
Solution Approach 2:
The active silicon bridge acts as an intermediary device between the two ASICs. It provides active signal regeneration and equalization functions within the bridge itself, eliminating the need for complex passive equalization circuits on each ASIC. The bridge mediates the signal transmission by actively compensating for channel effects, thereby simplifying the overall system design
2Reliability
If conventional D2D interfaces use long channels with high attenuation, then standard protocols can be used, but complex signal equalization techniques are required that are only available at mature process stages, delaying time to market
Solution Approach 1:
By changing the channel length parameter from millimeter-scale to micrometer-scale through the TSV architecture, the patent enables reliable signal transmission using simple digital logic available at early process development stages. This eliminates the waiting period for mature process techniques to become available, significantly reducing time to market while maintaining signal transmission reliability
Data Source
AI summary
A microelectronic system may include a substrate having a first surface, one or more interposers mounted to and electrically connected to the first surface, first and second application specific integrated circuits (ASICs) each at least partially overlying and electrically connected to one of the interposers, a plurality of high-bandwidth memory elements (HBMs) each at least partially overlying and electrically connected to one of the interposers, and an active silicon bridge mounted to and electrically connected to the first surface and providing an electrical connection between the first and second ASICs, the active silicon bridge having active microelectronic devices therein. The microelectronic system may be configured such that the first and second ASICs and the active silicon bridge each have a purely digital CMOS interface therein. A plurality of bumps providing the electrical connection between the ASICs and the active silicon bridge may be configured to receive serial data therethrough.