Active Silicon Bridge Layout for Short-Channel ASIC Interconnects
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Solution Overview
Problem
Conventional die-to-die interfaces in integrated circuits face challenges with long channel lengths, high attenuation, and Intersymbol Interference (ISI) distortion, requiring complex signal equalization techniques like FIR, CTLE, and DFE, which are not feasible at early process development stages.
Innovation Solution
The implementation of an active silicon bridge with a microelectronic system that reduces channel length to a few micrometers, using parallel connections and serializers/de-serializers to achieve high bandwidth with a purely digital CMOS interface, eliminating the need for complex equalization techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional long channel D2D interfaces are used, then bandwidth can be achieved, but attenuation and ISI distortion increase requiring complex equalization techniques
Solution Approach 1:
The patent changes the physical parameter of channel length from tens of millimeters to a few micrometers by using a three-dimensional stacked architecture with interposers. This parameter change fundamentally alters the signal propagation characteristics, eliminating attenuation and ISI issues that plague conventional long-channel interfaces, thereby removing the need for complex equalization techniques while maintaining high signal quality
Solution Approach 2:
The patent transitions from a conventional two-dimensional planar interface to a three-dimensional stacked architecture using interposers. By adding the vertical dimension through multi-layer stacking with through-silicon vias, the system achieves short channel lengths without increasing lateral footprint, thereby improving signal quality without requiring complex equalization
2Reliability
If complex equalization techniques like FIR, CTLE, and DFE are implemented, then signal quality improves, but power consumption and area increase
Solution Approach 1:
By changing the channel length parameter from tens of millimeters to micrometers through 3D stacking, the patent eliminates the fundamental causes of signal degradation. This removes the need for power-hungry equalization circuits while maintaining excellent signal quality, thereby dramatically reducing power consumption
3Reliability
If complex equalization techniques are used, then signal quality improves, but design complexity and time to market increase
Solution Approach 1:
The patent simplifies the interface design by changing the channel length parameter through 3D stacking, which eliminates the need for complex equalization algorithms and circuits. This parameter change reduces design complexity significantly while maintaining signal quality, and allows the interface to be implemented as a simple parallel or serial digital connection
Solution Approach 2:
The patent extracts and removes the complex equalization functionality from the interface design. By using short channels through 3D stacking, the equalization function becomes unnecessary and is completely removed from the system, simplifying both hardware and software design
4Ease of manufacture
If conventional D2D interfaces with large bump pitch are used, then manufacturing is simpler, but bandwidth per millimeter is reduced
Solution Approach 1:
The patent adds the vertical dimension through multi-layer stacking with interposers, enabling high-density interconnects through the thickness of the stack. This 3D approach allows small bump pitch and high bandwidth per millimeter while maintaining manufacturing feasibility through standard flip-chip and through-silicon via processes
Data Source
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AI summary
A microelectronic system may include a substrate having a first surface, one or more interposers mounted to and electrically connected to the first surface, first and second application specific integrated circuits (ASICs) each at least partially overlying and electrically connected to one of the interposers, a plurality of high-bandwidth memory elements (HBMs) each at least partially overlying and electrically connected to one of the interposers, and an active silicon bridge mounted to and electrically connected to the first surface and providing an electrical connection between the first and second ASICs, the active silicon bridge having active microelectronic devices therein. The microelectronic system may be configured such that the first and second ASICs and the active silicon bridge each have a purely digital CMOS interface therein. A plurality of bumps providing the electrical connection between the ASICs and the active silicon bridge may be configured to receive serial data therethrough.