Active Device Substrate Layout for Lower IR Drop in Micro LED Pixels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Micro LED display apparatus face issues with IR drop and parasitic capacitance due to high resistivity in semiconductor materials, which affect the efficient transfer of electric current and circuit layout efficiency.
Innovation Solution
An active device substrate design that includes a transfer wire connected through first and second connection structures to semiconductor patterns, utilizing a double gate thin film transistor structure to reduce IR drop and parasitic capacitance, with optimized circuit layout for high-resolution pixel circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor materials are used for active devices in pixel array substrate, then device functionality is achieved, but high resistivity causes IR drop problem
Solution Approach 1:
A transfer wire structure is introduced as an intermediary component between the semiconductor active devices and the pixel electrodes. The transfer wire includes a first wire portion and a second wire portion that provide low-resistance current paths, mediating the electrical connection and reducing IR drop while maintaining the functionality of the semiconductor materials.
Solution Approach 2:
The wire structure is configured to overlap with the semiconductor patterns in the vertical dimension, creating a three-dimensional arrangement. This spatial configuration allows the transfer wire to provide current transport paths that bypass the high-resistance semiconductor material, effectively reducing IR drop through dimensional optimization.
2Ease of manufacture
If conventional circuit layout is used, then manufacturing is simplified, but parasitic capacitance increases and affects circuit efficiency
Solution Approach 1:
The circuit layout transitions from a planar two-dimensional arrangement to a three-dimensional configuration where wire portions overlap with semiconductor patterns vertically. This dimensional change reduces parasitic capacitance by optimizing the spatial relationship between conductive elements while maintaining manufacturability through standard thin-film deposition processes.
Solution Approach 2:
The wire structure is segmented into multiple portions (first wire portion, second wire portion) with different orientations and functions. This segmentation allows optimization of current paths to minimize parasitic capacitance while maintaining ease of manufacture through modular fabrication steps.
3Manufacturing precision
If high-resolution pixel circuits are designed, then display quality improves, but circuit layout complexity and IR drop increase
Solution Approach 1:
The transfer wire structure utilizes vertical overlapping in the third dimension to provide current transport paths that are independent of the planar circuit layout. This allows high-resolution pixel circuits to be designed with reduced IR drop without proportionally increasing layout complexity, as the wire portions can be configured in the vertical dimension rather than requiring extensive planar routing.
Data Source
AI summary
An active device substrate including a substrate, a transfer wire, a first insulating layer, a second insulating layer, a first semiconductor pattern, a second semiconductor pattern, a first connection structure, a second connection structure, a first gate, a second gate, a third insulating layer, a first source/drain, and a second source/drain is provided. The first insulating layer is located above the transfer wire. The second insulating layer is located above the first insulating layer. The first semiconductor pattern and the second semiconductor pattern are located between the first insulating layer and the second insulating layer. The first connection structure and the second connection structure are located above the second insulating layer and electrically connected to the transfer wire. The first gate and the second gate respectively overlap the first semiconductor pattern and the second semiconductor pattern.