Active Surge Protection Structure with Digital Control
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Solution Overview
Problem
Existing surge protection designs for ICs, particularly in advanced CMOS technology, face issues with excessive heat and electrical overstress due to surge events, and passive discrete elements like TVS and MOSFET clamps can cause unnecessary power-on resets or malfunctions due to unregulated driving capabilities, while lacking effective active on-chip surge protection solutions.
Innovation Solution
An active surge protection structure with a multi-bit surge-to-digital converter and a power MOSFET clamp circuit that adjusts its protection flexibility based on digital signals generated by surge detection circuits, allowing for selective control of the clamp circuit's fingers to dissipate surge energy effectively, thereby preventing damage to core circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If passive discrete elements (TVS, GDT, MOV) are used for surge protection, then surge energy can be dissipated, but they are only applicable at board level and cannot provide on-chip protection
Solution Approach 1:
The patent integrates surge protection functionality directly into the IC chip by nesting the clamp circuit and surge-to-digital converter within the core circuit architecture. The clamp circuit is formed using on-chip transistors (e.g., PMOS transistors) that are part of the standard CMOS fabrication process, enabling surge protection at the chip level rather than requiring external discrete components.
2Reliability
If big MOSFET clamp is used for active surge protection, then residual surge energy can be dissipated, but unregulated driving capability causes unnecessary power-on reset or malfunction
Solution Approach 1:
The patent implements a surge-to-digital converter that detects surge events and converts them into digital signals. These digital signals provide feedback control to the clamp circuit, enabling regulated driving capability. The feedback mechanism allows the clamp circuit to activate only when surge events are detected, preventing unnecessary power-on resets and malfunctions while maintaining effective surge energy dissipation.
Solution Approach 2:
The clamp circuit transitions from a static, always-active design to a dynamic, conditionally-active design. The driving capability of the clamp circuit is dynamically adjusted based on real-time surge detection signals, allowing the system to optimize between protection effectiveness and operational stability by activating the clamp only when surges are present.
3Productivity
If advanced CMOS technology is used, then device integration is improved, but gate oxide becomes vulnerable to surge-induced heat and electrical overstress
Solution Approach 1:
The patent places the clamp circuit and surge detection mechanism directly on the chip before surge events can damage the core circuitry. The surge protection structure is pre-integrated into the IC design, allowing immediate response to surge events and preventing gate oxide damage before it occurs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances system stability and surge robustness by allowing adjustable protection based on surge levels, preventing unexpected power-on resets and malfunctions, and effectively dissipating surge energy within ICs, improving protection beyond conventional board-level surge protection.
Implementation Method 1
The voltage detect unit is connected between the power line, the high voltage level VDD and the low voltage level VSS for recognizing the surge event
Implementation Method 2
the clamp circuit is electrically connected with the power line and the surge-to-digital converter, and being disposed adjacent to the core circuit for dissipating surge energy when the surge event occurs on the power line
Data Source
AI summary
An active surge protection structure is provided between a power line and a core circuit, comprising a surge-to-digital converter and a clamp circuit. The surge-to-digital converter comprises a plurality of surge detection circuit. Each surge detection circuit detects a surge event occurring on the power line and generates a digital signal. The clamp circuit is disposed adjacent to the core circuit and electrically connected with the surge-to-digital converter and the power line where the core circuit is connected for dissipating surge energy. The clamp circuit receives and is driven by the digital signals from the surge-to-digital converter such that its protection flexibility can be achieved according to the digital signals. By employing the present invention, it is extraordinarily advantageous of improving system stability and achieving comprehensive surge protection with configuration of driving capability dependent on surge levels.