Active Terminator Circuit for Display Panel Signal Uniformity
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Solution Overview
Problem
Large-size display panels face signal decay issues due to overlong transmission distances, and existing dual-side gate driving methods that attempt to compensate for this often result in wider panel borders, which is undesirable.
Innovation Solution
A display panel design incorporating a shift register and an active terminator, where the active terminator includes transistors and capacitors to enhance gate driver capability and signal uniformity, eliminating the need for high voltage processes in manufacturing, thereby reducing manufacturing costs and maintaining a narrower panel border.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dual-side gate driving method is used to compensate signal decay, then signal uniformity is improved, but panel border width increases
Solution Approach 1:
The gate driving function is segmented between the shift register at one end and the active terminator at the other end of the gate line. This segmentation allows each component to perform a specific function: the shift register generates and transmits gate signals, while the active terminator compensates for signal decay, thereby achieving signal uniformity without requiring identical drivers on both borders and reducing the panel border width.
Solution Approach 2:
The active terminator is specifically designed with transistors and capacitors to provide localized signal compensation at the far end of the gate line. This local quality enhancement addresses the signal decay problem at the specific location where it occurs most severely, without requiring uniform distribution of complex driving circuits across the entire panel border.
2Reliability
If identical gate drivers are disposed on left and right borders to diminish signal decaying, then signal uniformity is improved, but panel border width increases
Solution Approach 1:
Instead of using symmetric dual-side gate driving circuits, the patent employs an asymmetric configuration where a shift register is placed at one end and an active terminator at the other end. This asymmetric design achieves signal decay compensation with reduced border area by distributing driving functions unevenly across the gate line rather than requiring identical circuits on both sides.
Solution Approach 2:
The active terminator serves multiple functions: it compensates for signal decay, maintains signal uniformity, and reduces the need for high voltage processes. By consolidating these functions into a single component at one border, the design avoids duplicating full gate driving circuits on both borders, thereby reducing the overall panel border area while maintaining reliability.
3Power
If high voltage process is used in fabrication, then driving capability is enhanced, but manufacturing cost increases
Solution Approach 1:
The active terminator uses capacitors and transistors configured to provide voltage boosting and signal reinforcement without requiring high voltage fabrication processes. By changing the circuit parameters and using standard voltage processes with carefully designed RC networks, the patent achieves enhanced driving capability while avoiding the increased manufacturing costs associated with high voltage process fabrication.
Data Source
AI summary
A display panel includes a shift register and an active terminator. The shift register has a drive circuit coupled to one end of a gate line. The active terminator is coupled to the other end of the gate line and includes a first transistor, a second transistor, and a first capacitor. The first transistor has a first terminal connected to a first clock signal, a second terminal connected to the gate line, and a third terminal. The second transistor has a first terminal connected to a first internal node, a second terminal connected to the third terminal of the first transistor, and a third terminal connected to a first DC voltage source. The first capacitor has a first terminal connected to the gate line and a second terminal connected to the third terminal of the first transistor and the second terminal of second transistor.