Active-to-Active IC Packaging with Redistribution Structure
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Solution Overview
Problem
Traditional integrated circuit packaging technologies fail to meet the demands of slim, compact, and multi-functional electronic devices, as they require smaller and thinner packaging solutions to enhance portability and performance while maintaining low costs and high efficiency.
Innovation Solution
The proposed integrated circuit packaging system involves a base carrier with a first integrated circuit and a second integrated circuit coupled in an active-to-active configuration, featuring a redistribution structure and a base encapsulation with a recess to expose the redistribution structure, which reduces package height and cost by eliminating the need for spacers and simplifying electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional single chip packaging technology is used, then manufacturing process is simple, but packaging size and thickness cannot be reduced to meet slim device requirements
Solution Approach 1:
The patent implements package-on-package (POP) architecture where a first chip package is nested within a second chip package. The first integrated circuit is mounted on a first carrier and the second integrated circuit is mounted on a second carrier that is attached to the first carrier, creating a nested configuration that reduces overall device footprint while maintaining functional separation and manufacturing simplicity.
Solution Approach 2:
The patent transitions from traditional planar single-chip packaging to three-dimensional stacked packaging. By stacking the first and second chip packages vertically with the first package beneath the second package, the design achieves reduced lateral dimensions (length and width) while managing complexity through vertical layering and standardized interconnection interfaces.
2Ease of manufacture
If solder is used to electrically connect two chip packages in conventional POP structure, then electrical connection is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent introduces an intermediary connection structure between the first and second integrated circuits. Instead of direct solder joints between chip packages, the design uses redistribution structures and interconnection elements that mediate the electrical connection, simplifying the manufacturing process while maintaining reliable electrical pathways through standardized interfaces and modular assembly.
3Volume of moving object
If package size is reduced for portability, then device compactness improves, but routing complexity and signal performance deteriorate
Solution Approach 1:
The patent segments the integrated circuit system into multiple separate chip packages (first and second packages) that are stacked vertically. This segmentation allows each package to have optimized, shorter internal routing paths while the overall system volume is reduced through vertical stacking. The segmentation also enables independent manufacturing and testing of each package, simplifying the overall manufacturing process despite the compact final form factor.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: providing a base carrier; providing a first integrated circuit having a first integrated circuit inactive side and a first integrated circuit active side; coupling a second integrated circuit, having a second integrated circuit inactive side and a second integrated circuit active side, to the first integrated circuit in an active-to-active configuration; attaching the first integrated circuit over the base carrier; attaching a redistribution structure over the first integrated circuit; and forming a base encapsulation over the redistribution structure, the base encapsulation having a recess partially exposing the redistribution structure.