Active Trace Assertion Verification System

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Solution Overview

Problem

Circuit designers face difficulties in tracing the source of assertion property violations in complex circuit designs, as existing simulation tools only provide information on when a property fails without indicating the cause, requiring manual analysis of both assertion statements and circuit designs.

Innovation Solution

A system that displays separate representations of each expression in a circuit simulation, annotates evaluation times, and highlights variables contributing to false evaluations, allowing users to trace the source of property violations and fulfillments through interactive displays and debugging tools.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If assertion based verification is used to evaluate circuit properties, then the ability to detect property violations is improved, but the difficulty of tracing the source of violations increases

Engineering Contradiction:
Improveproperty violation detectionVSAvoidtracing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the complex tracing problem by displaying separate representations of each expression in the assertion property. Each expression is evaluated independently and displayed separately, allowing users to trace violations expression-by-expression rather than analyzing the entire complex assertion at once. This segmentation reduces the cognitive load and makes the tracing process more manageable.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary display system that acts as a mediator between the circuit simulator and the user. This display shows intermediate evaluation results, variable values, and expression outcomes, providing a step-by-step breakdown of the property evaluation process. The intermediary display bridges the gap between the complex simulation data and the user's understanding, making traceability easier.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If detailed simulation data is collected to evaluate assertions, then the precision of property verification is improved, but the time required for analysis increases

Engineering Contradiction:
Improveproperty verification precisionVSAvoidanalysis time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary actions by pre-evaluating expressions and pre-identifying variable values during the simulation process. The system prepares and displays expression representations with their evaluation results in advance, so when a property violation occurs, the analysis is already partially complete. This reduces the time needed for post-simulation analysis while maintaining precise verification.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces manual mechanical analysis with automated computer-based evaluation and display generation. Instead of requiring users to manually trace through simulation data and evaluate expressions, the system automatically evaluates each expression, collects variable values, and generates the display representation. This substitution of automated processing for manual analysis significantly reduces analysis time while maintaining high precision.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10372854B2Active trace assertion based verification system
Publication Date: 2019.08.06 SYNOPSYS INC
  • US10372854B2 patent drawing
  • US10372854B2 patent drawing
  • US10372854B2 patent drawing

AI summary

A method is presented for responding to user input by displaying when a circuit has a property expressed by an assertion based on data indicating values of signals of the circuit at a succession of times. The assertion expresses the property as a first sequence of expressions, and separately defines for each expression a corresponding evaluation time relative to the succession of times at which the expression is to be evaluated. The circuit has the property only if every expression of the first sequence evaluates true at its corresponding evaluation time. The method includes displaying a representation of each expression of the first sequence and identifying each variable that caused that expression to evaluate false and distinctively marking that variable's symbol relative to other variable symbols within the display for each expression of the first sequence that evaluates false at its corresponding evaluation time.