Active Trench Field Plate Layout for Transistor Voltage Reliability
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Solution Overview
Problem
Existing power electronic transistors, such as silicon CoolMOS and IGBTs, face challenges in reliability due to limitations in the design of active cell fields and edge termination regions, which affect their performance and durability.
Innovation Solution
The transistor device incorporates a semiconductor substrate with elongate active trenches and mesas, featuring a field plate and gate electrode configuration, where the gate electrode is positioned above and insulated from the field plate, with specific depth and width ratios, and an edge termination structure with an edge field plate, optimized through a multi-step etching process to form the field plate and gate oxide.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the gate electrode is positioned closer to the field plate (smaller d2/d1 ratio), then the device complexity is reduced, but the insulation and voltage handling capability deteriorate
Solution Approach 1:
The patent applies parameter changes by optimizing the depth ratio d2/d1 to fall within the specific range of 1.005:1 to 2:1, and the insulating layer thickness ratio d3/d4 to fall within 1.01:1 to 3:1. These parameter optimizations simultaneously achieve adequate insulation and voltage handling capability while maintaining reasonable device complexity and manufacturability.
2Reliability
If the field plate width is increased, then the voltage handling capability is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent specifies the field plate width wfp should be in the range of 175 nm to 325 nm, representing an optimization of the geometric parameter that balances voltage handling capability with manufacturability. This parameter range achieves adequate voltage blocking while remaining compatible with standard fabrication processes.
3Productivity
If the active trench width is reduced, then the device integration density is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes the active trench width wt to be in the range of 1400 nm to 1900 nm, which balances device integration density with manufacturing precision. This parameter selection allows for higher integration while remaining achievable with conventional fabrication technologies.
4Reliability
If the edge termination structure is added, then the voltage handling capability is improved, but the device complexity increases
Solution Approach 1:
The patent divides the device into distinct functional regions: the cell field containing active trenches with field plates and gate electrodes, and the edge termination region with edge field plates. This segmentation allows each region to be optimized independently for its specific function while maintaining overall device reliability and manageable complexity.
Data Source
AI summary
A transistor device includes a semiconductor substrate having a first major surface, a cell field and an edge termination region laterally surrounding the cell field. The cell field includes: elongate active trenches that extend from the first major surface into the semiconductor substrate, a field plate and a gate electrode being positioned in each elongate active trench, the gate electrode being arranged above and electrically insulated from the field plate; and elongate mesas, each elongate mesa being formed between neighbouring elongate active trenches, the elongate mesas comprising a drift region, a body region on the drift region and a source region on the body region.