Active-Wafer Redistribution Layers to Reduce Package Warping

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Solution Overview

Problem

Existing semiconductor packages face challenges such as stress-induced warping of the package substrate, leading to issues like solder cold joints and bridging during surface mounting, particularly in high-performance computing applications, which complicate effective interconnection with support substrates.

Innovation Solution

The formation of redistribution layers directly on an active wafer or semiconductor die, eliminating the need for a separate interposer, reduces thermal expansion stresses and simplifies the fabrication process, allowing for a more modular and stress-resistant semiconductor device configuration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a separate interposer is used to form redistribution layers, then electrical interconnection is achieved, but thermal expansion stresses cause warping of the package substrate

Engineering Contradiction:
Improveelectrical interconnection reliabilityVSAvoidpackage substrate warping
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent extracts and eliminates the separate interposer component from the package structure. By forming redistribution layers directly on the active wafer, the invention removes the interposer that was causing thermal expansion mismatch and substrate warping, while maintaining electrical interconnection functionality through the directly-formed redistribution layers

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the functions of the active wafer and interposer into a single integrated structure. The redistribution layers are formed directly on the active wafer surface, combining what were previously separate components (wafer and interposer) into one unified package structure, thereby eliminating thermal expansion stresses between dissimilar materials

Inventive Principle:
Principle #5Merging (Combining)

2Adaptability or versatility

If a separate interposer is used, then redistribution of electrical connections is enabled, but the fabrication process becomes more complex

Engineering Contradiction:
Improveelectrical connection redistribution capabilityVSAvoidfabrication process complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The invention extracts and removes the separate interposer fabrication steps from the manufacturing process. By forming redistribution layers directly on the active wafer using standard semiconductor fabrication techniques, the process eliminates the need for separate interposer manufacturing, handling, and assembly steps, thereby simplifying the overall fabrication workflow

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent combines the redistribution layer formation process with the active wafer fabrication process. Instead of manufacturing redistribution layers on a separate interposer and then assembling them, the invention integrates both functions into a single fabrication sequence, reducing process complexity and improving manufacturing efficiency

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If multiple chips are stacked to improve integration density, then bandwidth and speed increase, but thermal expansion stresses and assembly difficulties increase

Engineering Contradiction:
Improveintegration density and bandwidthVSAvoidassembly complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple chip functions into a single integrated wafer structure with directly-formed redistribution layers. This approach enables high integration density and bandwidth similar to stacked configurations, but maintains a single-plane assembly that is simpler to manufacture and assemble compared to multi-chip stacking

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12482753B2Semiconductor device having redistribution layers formed on an active wafer and methods of making the same
Publication Date: 2025.11.25 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12482753B2 patent drawing
  • US12482753B2 patent drawing
  • US12482753B2 patent drawing

AI summary

An embodiment semiconductor device may include a semiconductor die; one or more redistribution layers formed on a surface of the semiconductor die and electrically coupled to the semiconductor die; and an active or passive electrical device electrically coupled to the one or more redistribution layers. The active or passive electrical device may include a silicon substrate and a through-silicon-via formed in the silicon substrate. The active or passive electrical device may be configured as an integrated passive device including a deep trench capacitor or as a local silicon interconnect. The semiconductor device may further include a molding material matrix formed on a surface of the one or more redistribution layers such that the molding material matrix partially or completely surrounds the active or passive electrical device.