DRAM Refresh Skip Signaling for Active Word Line Access

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Solution Overview

Problem

The increasing integration of DRAM cells leads to interference between adjacent cells, affecting data reliability and necessitating frequent refresh operations, which consume significant power and hinder system performance.

Innovation Solution

A memory device with a refresh control circuit that includes an active tagging latch to determine if a word line has been activated, allowing the system to skip refresh operations on active word lines, reducing power consumption and improving system efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If refresh operations are performed on all word lines periodically, then data reliability is maintained, but power consumption increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies local quality by differentiating refresh operations based on word line activity status. Active word lines (those currently being accessed) are excluded from refresh operations, while inactive word lines undergo standard periodic refresh. This localized differentiation maintains data reliability for inactive cells while reducing unnecessary power consumption on active word lines.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements dynamics by making the refresh operation adaptive to real-time access patterns. The system dynamically identifies which word lines are currently active based on access requests and adjusts the refresh schedule accordingly. This dynamic approach allows the system to transition between full refresh mode and selective skip mode based on actual workload conditions.

Inventive Principle:
Principle #15Dynamics

2Reliability

If refresh operations are performed frequently due to increased integration, then data reliability is maintained, but system performance deteriorates

Engineering Contradiction:
Improvedata reliabilityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies local quality by targeting refresh operations only to inactive word lines rather than uniformly refreshing all word lines. This localized approach maintains data reliability for cells that are not currently in use while eliminating redundant refresh operations on active word lines, thereby improving overall system performance.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements the skipping principle by allowing the refresh operation to skip inactive word lines during periodic refresh cycles. When a word line is identified as inactive (not currently being accessed), the system skips the refresh operation for that word line, reducing the total number of refresh operations required and improving system throughput.

Inventive Principle:
Principle #21Skipping (Rushing through)

3Reliability

If all word lines are refreshed uniformly, then data reliability is ensured, but timing constraints for read/write operations are limited

Engineering Contradiction:
Improvedata reliabilityVSAvoidtiming constraints
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies local quality by creating different treatment paths for active and inactive word lines. Inactive word lines undergo periodic refresh to maintain reliability, while active word lines are exempt from refresh operations during their active period. This differentiation eliminates timing constraints for read/write operations on active word lines, as they can proceed without waiting for refresh cycles.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20260073967A1Memory device, memory system including memory device, and method of operating memory device
Publication Date: 2026.03.12 SAMSUNG ELECTRONICS CO LTD
  • US20260073967A1 patent drawing
  • US20260073967A1 patent drawing
  • US20260073967A1 patent drawing

AI summary

A method of operating a memory device, the method includes periodically receiving a refresh command from a host, determining whether a target row address is activated during a predetermined period of time, and skipping a refresh operation on a word line corresponding to the target row address when the target row address is activated, and transmitting, to the host, a refresh skip signal corresponding to the word line on which the refresh operation is skipped, or performing, in response to the refresh command, a refresh operation on a word line corresponding to the target row address when the target row address is not activated.